PC87591L-N05 Datasheet, PDF (76/401 Pages) National Semiconductor (TI) – LPC Mobile Embedded Controller

4.0 Embedded Controller Modules (Continued)
begin
WAIT field in SZCFGn reg. ≠ 0
Address placed on A0-20;
SELn: activated.
T1
WAIT field in SZCFGn reg. = 0
TIW
Internal waits corresponding to WAIT field in SZCFGn register.
RD: active
Internal waits completed
T2
In SZCFGn reg.: {BW,WBR,BRE} = 001
Core attempts to read a word
In SZCFGn reg.:
BW = 0; {WBR,BRE} = 11;
Core attempts to read a word
Next address on A0-19;
End of T2B: Data sampled.
T2B
Next address
on A0-19
TBW
RD: active;
End of T2: Data is sampled.
In SZCFGn reg.: HOLD ≠ 0
{BW = 1 or BRE = 0
or core attempts to read a byte}
Other SZCFGn
configuration
T_hold
First T_hold : SELn
and RD are deactivated
Hold cycles according
to HOLD field in SZCFGn reg.
HOLD field in SZCFGn reg. ≠ 0
Hold cycles completed
HOLD field in SZCFGn reg. = 0
end
Address on A0-20 invalid/changed;
SELn and RD: inactive.
Figure 19. Normal Read Bus Cycle
Note: References to SZCFGn also apply to the IOCFG register.
References to SELn also apply to the SELIO signal.
TBW and T2B states do not exist in bus cycles of the IO zone.
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