PC87591L-N05 Datasheet, PDF (145/401 Pages) National Semiconductor (TI) – LPC Mobile Embedded Controller

4.0 Embedded Controller Modules (Continued)
Cycle Time Register (CTR)
The CTR register controls the cycle time and duty cycle steps, CTR is set (FFFF₁₆) on reset.
Location: 00 FD02₁₆
Type: R/W
Bit
Name
Reset
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CTR15-0
1111111111111111
Bit
Description
15-0
Cycle Time Value. The 8/16-bit down-counter divides the pre-scaler output clock either by CTR15-0 + 1 when
PWMRES bit (in PWMCNT register) is set to 1, or by CTR7-0 + 1 when PWMRES bit is set to 0. For example,
a value of 0000₁₆ results in a divide by 1, a value of FFFF₁₆ results in a divide by 65536.
When PWMRES bit is set to 0, only the low byte (CTR7-0) of this register must be written (CTR15-8 are
ignored).
The contents of this register may be changed only when the PWM module is in Low Power mode. Otherwise,
there may be unpredictable results.
Duty Cycle Registers 0 to 7 (DCRi)
The DCRi (i = 0 to 7) registers control the duty cycle of PWMi output signal. DCRi is cleared (0000₁₆) on reset.
Location: Channel 0 - 00 FD08₁₆
Channel 1 - 00 FD0A₁₆
Channel 2 - 00 FD0C₁₆
Channel 3 - 00 FD0E₁₆
Channel 4 - 00 FD10₁₆
Channel 5 - 00 FD12₁₆
Channel 6 - 00 FD14₁₆
Channel 7 - 00 FD16₁₆
Type: R/W
Bit
Name
Reset
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DCRi15-0
0000000000000000
Bit
Description
15-0
Duty Cycle Value. DCRi register defines the number of clocks for which PWMi is high (from the full cycle of the
PWMi cycle), when Inverse PWMi bit in PWM Polarity register is 0.
If the DCRi value > CTR value, PWMi signal is always low.
If DCRi value == CTR value, PWMi signal is always high.
When Inverse PWMi bit is 1, the value of PWMi is inverse.
When PWMRES bit is set to 0, only the low byte (DCRi7-0) of this register must be written (DCRi15-8 are ignored).
Revision 1.2
145
www.national.com