PC87591L-N05 Datasheet, PDF (181/401 Pages) National Semiconductor (TI) – LPC Mobile Embedded Controller

4.0 Embedded Controller Modules (Continued)
4.12.4 Operation
Initializing the DAC
The PC87591L-N05 wakes up after power-up with all the D/A channels disabled (DACEN0-3 bits in DACCTRL register are
cleared to 0). In this state, all DAC activities are halted, and its current consumption is reduced to zero.
DACDATn registers (n=0 to 3) must be initialized to 00₁₆, or according to the required output level, before setting DACEN0-3
in DACCTRL register to 1.
Enabling and Disabling the DAC
Enabling the DAC. Each channel of the DAC is enabled independently by setting its DACEN bit. After enabling, it settles to
the value stored in DACDATn register after the specified settling time.
Disabling the DAC. The DAC channels may be independently disabled in order to reduce current consumption by clearing
the corresponding DACENn (n=0 to 3) bit in DACCTRL register. In this case, the output pin drives 0V, even if the respective
DACDATn register does not contain 00₁₆.
All DAC channels are automatically disabled when entering Idle mode if ENIDLE bit in DACCTRL register is cleared to 0.
This happens regardless of the state of DACENn (n=0 to 3) bit in DACCTRL register. In this case, the DA0-3 outputs drive
0V.
If the ENIDLE bit is set to 1, entering the Idle mode does not affect DAC operation, and DA0-3 outputs drive the voltage level
set by DACDATn (n=0 to 3) registers.
4.12.5 DAC Registers
The DAC interfaces with the core using one control and four data registers. These registers are mapped to the core address
space, as defined in Appendix A on page 367.
DAC Register Map
Mnemonic
Register Name
DACCTRL DAC Control
DACDAT0 DAC Data Channel 0
DACDAT1 DAC Data Channel 1
DACDAT2 DAC Data Channel 2
DACDAT3 DAC Data Channel 3
Type
R/W
R/W
R/W
R/W
R/W
Revision 1.2
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