PC87591L-N05 Datasheet, PDF (149/401 Pages) National Semiconductor (TI) – LPC Mobile Embedded Controller

4.0 Embedded Controller Modules (Continued)
Asynchronous Mode
USART Asynchronous mode enables the device to communicate with other devices using two communication signals: trans-
mit (UTXDn) and receive (URXDn).
In Asynchronous mode, Transmit Shift register (TSFT) and Transmit Buffer register (UnTBUF) double buffer data for trans-
mission. To transmit a character, a data byte is loaded into UnTBUF register. The data is then transferred to TSFT register.
While TSFT register is shifting out the current character (LSB first) on the UTXDn pin, UnTBUF register is loaded by software
with the next byte to be transmitted. When TSFT completes transmitting the last stop bit of the current frame, the contents
of UnTBUF are transferred to TSFT register and the Transmit Buffer Empty flag (TBE) is set. The TBE flag is automatically
reset by the USART when the software loads a new character into UnTBUF register. During transmission, the XMIP bit is
set high by the USART. This bit is reset only after the USART has sent the last stop bit of the current character and UnTBUF
register is empty. UnTBUF register is a read/write register. TSFT register is not user accessible.
In Asynchronous mode, the input frequency to the USART is 16 times the baud rate, i.e., there are 16 clock cycles per bit
time. In Asynchronous mode, the baud rate generator is always used as the UART clock.
Receive Shift register (RSFT) and Receive Buffer register (UnRBUF) double buffer the data being received. The USART
receiver continually monitors the signal on the URXDn pin for a low level to detect the beginning of a start bit. On sensing
this low level, the USART waits for seven input clock cycles and samples again three times. If all three samples still indicate
a valid low, the receiver considers this to be a valid start bit, and the remaining bits in the character frame are each sampled
three times around the mid-bit position. For any bit following the start bit, the logic value is found by majority voting, i.e., the
two samples with the same value define the value of the data bit. Figure 52 shows the process of start-bit detection and bit
sampling. Serial data input on the URXDn pin is shifted into RSFT register. On receiving the complete character, the con-
tents of RSFT register are copied into UnRBUF register and Receive Buffer Full flag (RBF) is set. The RBF flag is automat-
ically reset when software reads the character from UnRBUF register. The RSFT register is not user accessible.
16 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 1
Sample
Sample
STARTBIT
DATA (LSB)
16 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 1
Sample
DATABIT
Figure 52. USART Asynchronous Communication
Synchronous Mode
The USART Synchronous mode enables the device to communicate with other devices using three communication signals:
transmit (UTXDn), receive (URXDn) and clock (USCLKn). In this mode, data bits are transferred synchronously using the
USART clock signal. As shown in Figure 53, the data is transmitted on the rising edge and received on the falling edge of
the clock. Data is transmitted and received with the LSB first.
Revision 1.2
149
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