PC87591L-N05 Datasheet, PDF (282/401 Pages) National Semiconductor (TI) – LPC Mobile Embedded Controller

5.0 Host Controller Interface Module (Continued)
When HSECM bit is set, host Software Event Status bit in WK_STS0 register and the core Software Event Status bit in
MSHES0 are both cleared by writing 1 to the core Software Event Status bit (MSHES0 register). This is useful when the
software event is used to interrupt the core and is handled by it (Figure 96B).
Module IRQ Wake-Up Event
A module IRQ wake-up event is defined as the leading edge of the IRQ assertion of the RTC.
To enable the IRQ of a specific logical device to trigger a wake-up event, the associated enable bit must be set to 1. This is
bit 4 of the Interrupt Number and Wake-Up on IRQ Enable register, located at index 70₁₆ in the configuration space of the
logical device (see Table 42 on page 301). When this bit is set, any IRQ assertion of the corresponding logical device acti-
vates the module IRQ wake-up event. Therefore, the module IRQ wake-up event is a combination of all IRQ signals of the
logical devices for which wake-up on IRQ is enabled.
When the event is detected as active, its associated status bit (bit 7 of WK0_STS register) is set to 1. If the associated enable
bit (bit 7 of WK_EN0 register) is also set to 1, the PWUREQ output is asserted and remains asserted until the status bit is
cleared.
Since V_DD powers IRQ generation of the logical devices, a module IRQ event can be activated only when V_DD is present
(see Section 6.1 on page 297 for a list of logical devices).
Modem Ring
High to low transitions on RI1 (or RI2) indicate the detection of a ring in an external modem and can be used as wake-up
events.
Telephone Ring
A telephone ring is detected by the MSWC by processing the raw signal coming directly from the telephone line into the
RING input pin. Detection of a pulse train, with a frequency higher than 16 Hz lasting at least 0.19 sec, is used as a wake-
up event.
The RING pulse-train detection is achieved by monitoring the falling edges on RING in time slots of 62.5 msec (a 16 Hz
cycle). A positive detection occurs if falling edges of RING are detected in three consecutive time slots, following a time slot
in which no RING falling edge is detected. This detection method guarantees the detection of a RING pulse train with fre-
quencies higher than 16 Hz. It filters out (does not detect) pulses of less than 10 Hz and may detect pulses between 10 Hz
and 16 Hz.
ACPI State Change and Legacy Off Events
The host may operate in either Legacy or ACPI mode. The operation mode is specified by the Power Button Mode bit in
SuperI/O Configuration D register (SIOCFD). When EICFGPBM bit in MSIEN2 register is set, a change to the Power Button
Mode bit generates an interrupt to the core. The core may read the value of the Power Button Mode bit, using CFGPBM bit
in MSWCTL2 register, to determine how to interpret the other power state request bits.
The Power Supply Off bit in SIOCFD register may be used in Legacy mode to indicate a request to turn power off. A write
of 1 to this bit sets CFGPSO bit in MSWCTL2 register; then, if EICFGPSO bit in MSIEN2 register is set, an interrupt to the
core is generated, indicating the event.
A set of System State Change Request bits (S1-S5) are provided in WK_STATE register. The host uses these bits for ACPI-
compliant state change requests. A write of 1 to any of these bits indicates a state change request to the core through the
respective bit in MSWCTL2 register. When all bits in WK_STATE are written with 0, a request of S0 is indicated, and ACPIS0
bit in MSWCTL2 register is set. When any S0-S5 bit in MSWCTL2 is set and the respective mask bit in MSIEN2 register is
set, an interrupt to the core is generated whenever a change to any of the state bits is detected.
All interrupt requests may be cleared by writing 1 to the corresponding status bit or by masking the event (by clearing the
corresponding Interrupt Enable bit).
RTC Alarm
The RTC module may generate an ALARM signal (see Section 6.2.8 on page 321). The RTC alarm can serve as a wake-
up request to wake up the system; the request is routed to the core, which then wakes up the system. To enable an alarm
wake-up, the following settings should be made:
• Set the Alarm conditions in the RTC module. By masking the various interrupts, software may select a wake-up either
to the host directly, using the RTC’s IRQ, or to the core through the Alarm signal.
• Enable the Wake-Up on Alarm status interrupt masking (optional, for Interrupt Enabled mode) by setting EIRTCAL bit
in MSIEN2 register.
• Verify that the RTCAL bit in MSWCTL3 bit is cleared (no pending Alarm request).
• Enable the Wake-Up on MSWC event in the MIWU and ICU modules.
• Verify that the ALARM bit in the RTC is cleared.
After an ALARM event is detected in the RTC, the RTC ALARM status bit is set (bit 5 in CRC register, page 331); in re-
sponse, RTCAL bit in MSWCTL3 register is set.
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