PC87591L-N05 Datasheet, PDF (53/401 Pages) National Semiconductor (TI) – LPC Mobile Embedded Controller

2.0 Signal/Pin Description and Configuration (Continued)
Bit
Description
2 EXMEM16 (16-bit-Wide Expansion Memory). This bit enables the use of the 16-bit-wide expansion memory,
when the ENEMEM is set. The bus width indicated in this register should be the same as the bus width defined
in zone 0 and zone 2 of the BIU (SEL0, SEL2).
0: The External Memory to be eight bits wide
1: Enables the use of a 16-bit-wide External Memory
4-3 CLKOM (Clock Out Mode). This field selects the mode of operation of the CLKOUT signal. This field is in effect
only when this signal is set for output.
Bits
43
Description
0 0: Reserved (default)
0 1: CLK - a clock at the core frequency is driven out
1 0: 32.768 KHz clock output
1 1: Reserved
5 ENZONE2 (Enable Expansion Memory Zone 2). When set, this bit enables the use of BIU Zone 2 (SEL2) and
the associated address (selected by bits 0-1 of the PTWRH register; see Page 55) and data lines for the
interface with flash or SRAM devices. Use BIU Zone 2 configuration to select the access parameters to the
expansion memory and its width. When cleared, the associated address range is used with Zone 0 (SEL0).
0: Zone 2 (SEL2) is disabled. Zone 0 (SEL0) is used for 00 1000₁₆ − 00 DFFF₁₆ Expansion Memory address
range.
1: Zone 2 (SEL2) is enabled. The Expansion Memory address range is selected by bits 0-1 of the PTWRH register.
6 HOSTWAIT (Host Interface WAIT state). The host interface is in wait state after host domain power-up until
the bit is cleared by software (Booter). LPC transactions to the device during this state are extended by a valid
SYNC field (long wait state, LAD3:0 are 0110b). This bit is a sticky bit; it is set by core domain reset, and
remains set until explicitly cleared by software by writing 1b. Writing 0b to the bit has no effect. On clearing the
HOSTWAIT bit, the host interface is released from wait state.
7 GTMON (Go-to Target Monitor Set Flag). This bit is set to indicate that the code should jump to the beginning
of the Target Monitor (TMON). The reset routine of the application should check this bit and behave accordingly.
GTMON bit is used by the Booter firmware,; therefore it should not be modified by the application firmware (EC
BIOS). Once cleared, this bit can not be set by software.
External Interrupts Configuration Register (EICFG)
The EICFG register is a read/write, byte-wide register. It enables the use of some of the external interrupts. The EICFG bits
have impact only when the pin is configured to its GPIO function. EICFG is cleared (00₁₆) on reset.
Note that some of the pins that have an external interrupt (not controlled by the EICFG register) have an alternate function
that is an input. When a pin’s alternate function is selected, its interrupt function is also enabled.
The format of EICFG is as follows:
Location: 00 FF00₁₆
Type: R/W
Bit
Name
Reset
7
6
5
4
3
2
1
0
Reserved
EXWINT46 EXWINT45
0
0
0
0
0
0
0
0
Bit
Description
0 EXWINT45 (Enable EXWINT45).
0: EXWINT45 input is blocked (disabled) while not being read as a GPIO (default)
1: EXWINT45 input is open; this enables the detection of changes on the input to trigger interrupts
Revision 1.2
53
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