PC87591L-N05 Datasheet, PDF (6/401 Pages) National Semiconductor (TI) – LPC Mobile Embedded Controller

Table of Contents
Features............................................................................................................................................................. 2
Embedded Controller System Features ................................................................... 2
Host Controlled Functions Features ......................................................................... 3
Clocking, Supply and Package Information .............................................................. 3
Revision Record .............................................................................................................................................. 5
1.0 Introduction
1.1 DOCUMENT ORGANIZATION .................................................................................................. 23
1.2 GENERAL DESCRIPTION ........................................................................................................ 23
1.2.1 System Connections .................................................................................................... 23
1.2.2 Power Management .................................................................................................... 23
1.2.3 Operating Environments .............................................................................................. 25
1.3 INTERNAL ARCHITECTURE .................................................................................................... 25
1.3.1 Processing Unit ........................................................................................................... 26
1.3.2 Bus Interface Unit and Memory Controller (BIU) ......................................................... 26
1.3.3 Memory ........................................................................................................................ 26
1.3.4 Peripherals ................................................................................................................. 26
1.3.5 Host-Controller Interface Modules ............................................................................... 27
1.3.6 Host-Controlled SuperI/O Modules and Host Interface ............................................... 28
1.4 OPERATING ENVIRONMENTS ................................................................................................ 28
1.4.1 IRE Environment ......................................................................................................... 28
1.4.2 OBD Environment ....................................................................................................... 29
1.4.3 DEV Environment ........................................................................................................ 29
1.5 MEMORY MAP .......................................................................................................................... 29
1.5.1 Core Address Domain Memory Map ........................................................................... 29
Register Abbreviations and Access ........................................................................ 32
Accessing Base Memory ........................................................................................ 33
Accessing Expansion Memory ............................................................................... 33
Accessing I/O Expansion Space ............................................................................ 34
1.5.2 Host Address Domain Memory Map ............................................................................ 34
1.5.3 Core Access to Host Controlled Peripherals ............................................................... 35
2.0 Signal/Pin Description and Configuration
2.1 CONNECTION DIAGRAMS ................................................................................................ 36
2.2 BUFFER TYPES AND SIGNAL/PIN DIRECTORY .................................................................... 38
2.2.1 ACCESS.bus Interface ............................................................................................... 38
2.2.2 Analog Interface ........................................................................................................ 39
2.2.3 Clocks ........................................................................................................................ 39
2.2.4 Core Bus Interface Unit (BIU) .................................................................................... 39
2.2.5 Development System Support .................................................................................... 40
2.2.6 General-Purpose I/O (GPIO) and Internal Keyboard Scan ....................................... 41
2.2.7 Host Interface ............................................................................................................. 42
2.2.8 Interrupt and Wake-Up Inputs (ICU and MIWU) ......................................................... 44
2.2.9 Power and Ground ..................................................................................................... 44
2.2.10 PS/2 Interface ............................................................................................................ 45
2.2.11 Strap Configuration and Testing ................................................................................ 45
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Revision 1.2