PC87591L-N05 Datasheet, PDF (256/401 Pages) National Semiconductor (TI) – LPC Mobile Embedded Controller

5.0 Host Controller Interface Modules (Continued)
5.2.3 Core PM Registers
For a summary of the abbreviations used for Register Type, see “Register Abbreviations and Access” on page 32.
Core PM Register Map
Mnemonic
Register Name
HIPMnST^{1 Host Interface PM n Status}
HIPMnDO^{1 Host Interface PM n Data Out Buffer}
HIPMnDOC^{1 Host Interface PM n Data Out Buffer with SCI}
HIPMnDOM^{1 Host Interface PM n Data Out Buffer with SMI}
HIPMnDI¹
Host Interface PM n Data In Buffer
HIPMnDIC^{1 Host Interface PM n Data In Buffer with SCI}
HIPMnCTL^{1 Host Interface PM n Control}
HIPMnIC¹
Host Interface PM n Interrupt Control
HIPMnIE¹
Host Interface PM n Interrupt Enable
1. Where n stands for register 1 or 2.
Type
Varies per bit
WO
WO
WO
RO
RO
R/W
R/W
R/W
Host Interface PM n Status Register (HIPMnST)
The HIPMnST register contains the status of the host interface PM channel buffers (DBBIN and DBBOUT). It also provides
a means for the PC87591L-N05 to send status bits to the host. This register is read by a host processor read operation from
address 66₁₆. HIPMnST is cleared on reset.
Location: Channel 1 - 00 FEAC₁₆
Channel 2 - 00 FEBE₁₆
Type: Varies per bit
Bit
Name
Reset
7
6
5
4
3
2
1
0
ST3-ST0
A2
F0
IBF
OBF
0
0
0
0
0
0
0
0
Bit Type
Description
0
RO OBF (Output Buffer Full). The bit is set when the PM channel’s DBBOUT is written to by the core
(writing to HIPMnDO, HIPMnDOM or HIPMnDOC register). The bit is cleared by a host processor read
of the output buffer (62₁₆). Writing to this bit is ignored.
1
RO IBF (Input Buffer Full). The bit is set when the PM channel’s DBBIN is written to by the host
processor (writing to either address 62₁₆ or address 66₁₆). The bit is cleared by a core read of the PM
input buffer (HIPMnDI or HIPMnDIC).
2
R/W F0 (Flag 0). General-purpose flag that can be set or cleared by the core firmware.
3
RO A2 (A2 Address). Indicates whether the last write operation of the host to the PMn channel was to the
data register or the Command register. Writing to this bit is ignored.
0: Last write was to the data register (pointed to by configuration register index 60₁₆ and 61₁₆) (default)
1: Last write was to the command register (pointed to by configuration register index 62₁₆ and 63₁₆)
7-4 R/W ST3-ST0 (Status). Four general-purpose flags that can be used for signaling between the host and
core. When used as an embedded controller interface channel for ACPI, a predefined meaning is
assigned to ST0, ST1 and ST2. The standard meaning is BURST, SCI event and SMI event,
respectively.
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