PC87591L-N05 Datasheet, PDF (61/401 Pages) National Semiconductor (TI) – LPC Mobile Embedded Controller

3.0 Power, Reset and Clocks (Continued)
Analog
Power
(3.3V)
Suspend
Digital
Power
(3.3V)
Host
Digital
Power
(3.3V)
VIN0 _{AD0 KBSIN0}
KBVIN0
V_IN
VIN9
KBSIN7
AD9
KBVIN7
KBV_IN
VOUT0
VOUT3
PC87591L-N05
DA0
V_CORF
DA3
V_BAT
ZL
L₁
10-100 µH
C1 ⁺ _C2
22 ^0.1
µF µF
AV_CC
AGND
V_DD
V_CC
GND
Backup Power
C7
0.1
C5 ^{+ µF}
C6
+ C4
0.1
µF
C3
0.1
µF
22
µF
22
µF
BAT
C8
1
µF
Analog Ground Plane
Digital Ground Plane
Figure 9. PC87591L-N05 Power Supply Connection
3.2 RESET SOURCES AND TYPES
The PC87591L-N05 has several input reset types:
• V_PP Power-Up reset (for V_PP supplied functions only)
Activated when either V_CC or V_BAT is powered up after both have been off.
• V_CC Power-Up reset
Activated when V_CC is powered up.
• Warm reset
Activated on RESET1 input falling edge.
• Watchdog and Debugger Interface resets:
— Watchdog reset
Activated on request from the TWD module (watchdog signal is asserted); see Section 4.10 on page 160.
— Debugger Interface reset
Activated on request from the Debugger Interface module used during debug and flash updates; see Section 4.19
on page 221.
• Host Domain reset
This is divided into two sub-groups: Host Domain Hardware and Host Domain Software reset. Combinations consist-
ing of the flowing events are used to trigger these reset operations:
— RESET1 active
— When V_DD is active, RESET2 is active
— On V_DD power-up
— A Software reset triggered by a write of 1 to bit 1 of SIOCF1 register in the SuperI/O Configuration registers; see
Section 6.1.8 on page 306
Revision 1.2
61
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