PC87591L-N05 Datasheet, PDF (238/401 Pages) National Semiconductor (TI) – LPC Mobile Embedded Controller

4.0 Embedded Controller Modules (Continued)
Transaction Effect on the External Bus
The following core bus transactions are reflected on the external bus:
• Accesses to external zones of expansion memory, off-chip base memory and accesses that use the I/O Expansion
protocol are indicated by the active state of the SEL0, SEL12 and SELIO signals, respectively, and are described by
the address and data buses and the status signals, BST2-0.
• Accesses to on-chip memories and peripheral modules can be observed using the “Core Bus Monitoring Bus Cycles”
(see “Core Bus Monitoring” on page 80). They accesses are indicated by an inactive state for the SEL0, SEL12
and/or SELIO signals. They are described by addresses A0-20, the byte-enable BE0-1 signals, the CBRD signal and
the BST2-0 signals.
• BE0 is high when a lower memory byte (a byte in an even address) is accessed. BE1 is high when a higher memory
byte (a byte in an odd address) is accessed.
• CBRD is high when the transaction is a read operation and low when it is a write operation.
Pipe Status Signals (PFS and PLI)
The PFS indicates the completion of an instruction in the core. The Pipe Long Instruction (PLI) signal indicates the size of
the completed instruction, where 0 = word instruction and 1 = double-word instruction (see Figure 83). If an instruction flush-
es the pipeline, the fetch for the next instruction (BST=101) is issued during the cycle following the instruction’s PFS, or later.
Instruction i
Completed
Instruction i+1
Completed
CLK
PFS
PLI
Figure 83. Pipe Status Signal (PFS and PLI)
4.20.7 On-Chip Hardware Breakpoint
The core provides two types of hardware breakpoints:
• Address Match - Detection of a matched address for the current executed instruction (PC value)
• Data Match - Detection of a read or write transaction for a matched memory location
For a detailed description of the core breakpoint mechanism, refer to the CR16B User Manual.
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