PC87591L-N05 Datasheet, PDF (62/401 Pages) National Semiconductor (TI) – LPC Mobile Embedded Controller

3.0 Power, Reset and Clocks (Continued)
Unless otherwise noted, reset references throughout the PC87591L-N05 modules default to the following types:
• For V_PP retained functions: V_PP Power-Up reset
• For core domain functions and host-core interface functions: V_CC Power-Up reset, Warm reset, Watchdog reset, De-
bugger Interface reset and Software reset
• For host domain functions: Host Domain reset
In DEV environment, the PC87591L-N05 outputs to the BRKL_RSTO signal an indication that a reset occurred at the core
domain. See Section 4.20.3 on page 236 for the implementation and usage of RSTO.
The following sections detail the sources and effects of the various resets on the PC87591L-N05, per reset type.
3.2.1 V_PP Power-Up Reset
V_PP is an internal power signal derived from V_CC and V_BAT. V_PP Power-Up reset is generated by an internal circuit that de-
tects the status of the V_PP power. V_PP Power-Up reset signal is active from the rising of V_PP until the V_PP power is detected
as “good” (i.e., V_PP is above V_BATDTC). When active, this signal resets all registers whose values are retained by V_PP.
For more details, see Section 6.2.9 on page 322.
3.2.2 V_CC Power-Up Reset
V_CC Power-Up reset is generated by an internal circuit. The PC87591L-N05 performs a V_CC Power-Up reset when V_CC pow-
er is applied. This reset is completed t_IRST after the internal clocks have stabilized (see Section 7.6.2 on page 345).
If the 32 KHz crystal is disabled before V_CC power-up, external devices should wait at least t_32KW before accessing the
PC87591L-N05. Any host processor access during this time results in:
• The host processor is stalled (by driving a “Long WAIT sync” response on the LPC bus) until after the reset process
is completed (after the HOSTWAIT bit in MCFG register is set to 1 by the Booter firmware) and the bus request can
be performed.
• If HRAPU bit in MSWCTL1 register is set (1), the host processor is reset by asserting KBRST until the internal reset
is completed.
On V_CC Power-Up reset, the PC87591L-N05 responds as follows:
• Enables the 32 KHz crystal, if it is disabled.
• Resets the High-Frequency Clock Generator (HFCG) to its default frequency.
• Loads default values to all registers whose values are retained by V_CC.
• Puts pins with strap options into TRI-STATE and enables the internal pull-downs on the strap pins.
• Samples the values of the strap pins.
• Resets the TAP controller of the Debugger Interface module.
• Resets the MSWC, excluding those MSWC registers whose values are retained by V_PP.
• Resets Port PC0.
• Carries out all the Warm reset actions (see below).
3.2.3 Watchdog Reset and Debugger Interface Reset
The PC87591L-N05 generates a Watchdog reset on request from the TWD module (i.e., a watchdog signal is asserted). It
generates a Debugger Interface reset on request from the Debugger Interface module (reset command). During these re-
sets, the PC87591L-N05 performs the V_CC Power-Up reset actions, with the following exceptions:
• The PC87591L-N05 does not sample the value of any strap pin; instead, it maintains the configuration determined by
the strap pins at V_CC Power-Up reset.
• It does not reset the TAP controller.
• On Debugger I/F, reset PC0 is not reset (it is reset on Watchdog reset).
• It resets the HFCG to its default frequency.
• Some MSWC registers do not reset on Watchdog or Debugger I/F reset.
The reset periods are identical to the V_CC Power-Up reset period.
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