COP8AME9 Datasheet, PDF (69/83 Pages) National Semiconductor (TI) – 8-Bit CMOS Flash Microcontroller with 8k Memory, Dual Op Amps, Virtual EEROM, Temperature Sensor,10-Bit A/D and Brownout Reset

21.0 Memory Map (Continued)
Address
S/ADD REG
xxED
xxEE
xxEF
xxF0 to FB
xxFC
xxFD
xxFE
xxFF
0100 to 017F
0200 to 027F
0300 to 037F
Contents
Timer T1 Autoload Register T1RA Upper
Byte
CNTRL Control Register
PSW Register
On-Chip RAM Mapped as Registers
X Register
SP Register
B Register
S Register
On-Chip 128 RAM Bytes
On-Chip 128 RAM Bytes
On-Chip 128 RAM Bytes
Note: Reading memory locations 0070H–007FH (Segment 0) will return all
ones. Reading unused memory locations 0080H–0093H (Segment 0)
will return undefined data. Reading memory locations from other Seg-
ments (i.e., Segment 4, Segment 5, … etc.) will return undefined data.
22.0 Instruction Set
22.1 INTRODUCTION
This section defines the instruction set of the COP8 Family
members. It contains information about the instruction set
features, addressing modes and types.
22.2 INSTRUCTION FEATURES
The strength of the instruction set is based on the following
features:
• Mostly single-byte opcode instructions minimize program
size.
• One instruction cycle for the majority of single-byte in-
structions to minimize program execution time.
• Many single-byte, multiple function instructions such as
DRSZ.
• Three memory mapped pointers: two for register indirect
addressing, and one for the software stack.
• Sixteen memory mapped registers that allow an opti-
mized implementation of certain instructions.
• Ability to set, reset, and test any individual bit in data
memory address space, including the memory-mapped
I/O ports and registers.
• Register-Indirect LOAD and EXCHANGE instructions
with optional automatic post-incrementing or decrement-
ing of the register pointer. This allows for greater effi-
ciency (both in cycle time and program code) in loading,
walking across and processing fields in data memory.
• Unique instructions to optimize program size and
throughput efficiency. Some of these instructions are:
DRSZ, IFBNE, DCOR, RETSK, VIS and RRC.
22.3 ADDRESSING MODES
The instruction set offers a variety of methods for specifying
memory addresses. Each method is called an addressing
mode. These modes are classified into two categories: op-
erand addressing modes and transfer-of-control addressing
modes. Operand addressing modes are the various meth-
ods of specifying an address for accessing (reading or writ-
ing) data. Transfer-of-control addressing modes are used in
conjunction with jump instructions to control the execution
sequence of the software program.
22.3.1 Operand Addressing Modes
The operand of an instruction specifies what memory loca-
tion is to be affected by that instruction. Several different
operand addressing modes are available, allowing memory
locations to be specified in a variety of ways. An instruction
can specify an address directly by supplying the specific
address, or indirectly by specifying a register pointer. The
contents of the register (or in some cases, two registers)
point to the desired memory location. In the immediate
mode, the data byte to be used is contained in the instruction
itself.
Each addressing mode has its own advantages and disad-
vantages with respect to flexibility, execution speed, and
program compactness. Not all modes are available with all
instructions. The Load (LD) instruction offers the largest
number of addressing modes.
The available addressing modes are:
• Direct
• Register B or X Indirect
• Register B or X Indirect with Post-Incrementing/
Decrementing
• Immediate
• Immediate Short
• Indirect from Program Memory
The addressing modes are described below. Each descrip-
tion includes an example of an assembly language instruc-
tion using the described addressing mode.
Direct. The memory address is specified directly as a byte in
the instruction. In assembly language, the direct address is
written as a numerical value (or a label that has been defined
elsewhere in the program as a numerical value).
Example: Load Accumulator Memory Direct
LD A,05
Reg/Data
Memory
Accumulator
Memory Location
0005 Hex
Contents
Before
XX Hex
A6 Hex
Contents
After
A6 Hex
A6 Hex
Register B or X Indirect. The memory address is specified
by the contents of the B Register or X register (pointer
register). In assembly language, the notation [B] or [X] speci-
fies which register serves as the pointer.
Example: Exchange Memory with Accumulator, B Indirect
X A,[B]
Reg/Data
Memory
Accumulator
Memory Location
0005 Hex
B Pointer
Contents
Before
01 Hex
87 Hex
05 Hex
Contents
After
87 Hex
01 Hex
05 Hex
Register B or X Indirect with Post-Incrementing/
Decrementing. The relevant memory address is specified
by the contents of the B Register or X register (pointer
register). The pointer register is automatically incremented
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