COP8AME9 Datasheet, PDF (24/83 Pages) National Semiconductor (TI) – 8-Bit CMOS Flash Microcontroller with 8k Memory, Dual Op Amps, Virtual EEROM, Temperature Sensor,10-Bit A/D and Brownout Reset

11.0 In-System Programming
11.1 INTRODUCTION
This device provides the capability to program the program
memory while installed in an application board. This feature
is called In System Programming (ISP). It provides a means
of ISP by using the MICROWIRE/PLUS, or the user can
provide his own, customized ISP routine. The factory in-
stalled ISP uses the MICROWIRE/PLUS port. The user can
provide his own ISP routine that uses any of the capabilities
of the device, such as USART, parallel port, etc.
11.2 FUNCTIONAL DESCRIPTION
The organization of the ISP feature consists of the user flash
program memory, the factory boot ROM, and some registers
dedicated to performing the ISP function. See Figure 12 for
a simplified block diagram. The factory installed ISP that
uses MICROWIRE/PLUS is located in the Boot ROM. The
size of the Boot ROM is 1K bytes and also contains code to
facilitate in system emulation capability. If a user chooses to
write his own ISP routine, it must be located in the flash
program memory.
11.3 REGISTERS
There are six registers required to support ISP: Address
Register Hi byte (ISPADHI), Address Register Low byte
(ISPADLO), Read Data Register (ISPRD), Write Data Reg-
ister (ISPWR), Write Timing Register (PGMTIM), and the
Control Register (ISPCNTRL). The ISPCNTRL Register is
not available to the user.
11.3.1 ISP Address Registers
The address registers (ISPADHI & ISPADLO) are used to
specify the address of the byte of data being written or read.
For page erase operations, the address of the beginning of
the page should be loaded. For mass erase operations,
0000 must be placed into the address registers. When read-
ing the Option register, FFFF (hex) should be placed into the
address registers. Registers ISPADHI and ISPADLO are
cleared to 00 on Reset. These registers can be loaded from
either flash program memory or Boot ROM and must be
maintained for the entire duration of the operation.
Note: The actual memory address of the Option Register is
1FFF (hex), however the MICROWIRE/PLUS ISP routines
require the address FFFF (hex) to be used to read the
Option Register when the Flash Memory is secured.
TABLE 4. High Byte of ISP Address
ISPADHi
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2
Addr 15 Addr 14 Addr 13 Addr 12 Addr 11 Addr 10
Bit 1
Addr 9
Bit 0
Addr 8
TABLE 5. Low Byte of ISP Address
Bit 7
Addr 7
Bit 6
Addr 6
Bit 5
Addr 5
ISPADLO
Bit 4 Bit 3
Addr 4 Addr 3
Bit 2
Addr 2
Bit 1 Bit 0
Addr 1 Addr 0
20006317
FIGURE 12. Block Diagram of ISP
As described in Section 10.5 OPTION REGISTER, there is a
bit, FLEX, that controls whether the device exits RESET
executing from the flash memory or the Boot ROM. The user
must program the FLEX bit as appropriate for the applica-
tion. In the erased state, the FLEX bit = 0 and the device will
power-up executing from Boot ROM. When FLEX = 0, this
assumes that either the MICROWIRE/PLUS ISP routine or
external programming is being used to program the device. If
using the MICROWIRE/PLUS ISP routine, the software in
the boot ROM will monitor the MICROWIRE/PLUS for com-
mands to program the flash memory. When programming
the flash program memory is complete, the FLEX bit will
have to be programmed to a 1 and the device will have to be
reset, either by pulling external Reset to ground or by a
MICROWIRE/PLUS ISP EXIT command, before execution
from flash program memory will occur.
If FLEX = 1, upon exiting Reset, the device will begin ex-
ecuting from location 0000 in the flash program memory. The
assumption, here, is that either the application is not using
ISP, is using MICROWIRE/PLUS ISP by jumping to it within
the application code, or is using a customized ISP routine. If
a customized ISP routine is being used, then it must be
programmed into the flash memory by means of the
MICROWIRE/PLUS ISP or external programming as de-
scribed in the preceding paragraph.
11.3.2 ISP Read Data Register
The Read Data Register (ISPRD) contains the value read
back from a read operation. This register can be accessed
from either flash program memory or Boot ROM. This regis-
ter is undefined on Reset.
TABLE 6. ISP Read Data Register
Bit 7
Bit7
Bit 6
Bit6
Bit 5
Bit5
ISPRD
Bit 4 Bit 3
Bit4 Bit3
Bit 2
Bit2
Bit 1
Bit1
Bit 0
Bit0
11.3.3 ISP Write Data Register
The Write Data Register (ISPWR) contains the data to be
written into the specified address. This register is undeter-
mined on Reset. This register can be accessed from either
flash program memory or Boot ROM. The Write Data register
must be maintained for the entire duration of the operation.
Bit 7
Bit7
TABLE 7. ISP Write Data Register
Bit 6
Bit6
Bit 5
Bit5
ISPWR
Bit 4 Bit 3
Bit4 Bit3
Bit 2
Bit2
Bit 1
Bit1
Bit 0
Bit0
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