COP8AME9 Datasheet, PDF (23/83 Pages) National Semiconductor (TI) – 8-Bit CMOS Flash Microcontroller with 8k Memory, Dual Op Amps, Virtual EEROM, Temperature Sensor,10-Bit A/D and Brownout Reset

10.0 Functional Description
(Continued)
flags. In addition to the SC and R/C instructions, ADC,
SUBC, RRC and RLC instructions affect the Carry and Half
Carry flags.
10.9.3 ICNTRL Register (Address X'00E8)
Unused LPEN T0PND T0EN µWPND µWEN
Bit 7
T1PNDB
T1ENB
Bit 0
The ICNTRL register contains the following bits:
LPEN L Port Interrupt Enable (Multi-Input
Wake-up/Interrupt)
T0PND Timer T0 Interrupt pending
T0EN Timer T0 Interrupt Enable (Bit 12 toggle)
µWPND MICROWIRE/PLUS interrupt pending
µWEN Enable MICROWIRE/PLUS interrupt
T1PNDB Timer T1 Interrupt Pending Flag for T1B capture
edge
T1ENB Timer T1 Interrupt Enable for T1B Input capture
edge
10.9.4 T2CNTRL Register (Address X'00C6)
T2C3
Bit 7
T2C2
T2C1
T2C0
T2PNDA T2ENA T2PNDB T2ENB
Bit 0
The T2CNTRL register contains the following bits:
T2C3 Timer T2 mode control bit
T2C2 Timer T2 mode control bit
T2C1 Timer T2 mode control bit
T2C0
Timer T2 Start/Stop control in timer
modes 1 and 2, Timer T2 Underflow Interrupt
Pending Flag in timer mode 3
T2PNDA Timer T2 Interrupt Pending Flag (Autoreload
RA in mode 1, T2 Underflow in mode 2, T2A
capture edge in mode 3)
T2ENA Timer T2 Interrupt Enable for Timer Underflow
or T2A Input capture edge
T2PNDB Timer T2 Interrupt Pending Flag for T2B cap-
ture edge
T2ENB Timer T2 Interrupt Enable for T2B Input capture
edge
10.9.5 T3CNTRL Register (Address X'00B6)
T3C3
Bit 7
T3C2
T3C1
T3C0
T3PNDA
T3ENA T3PNDB T3ENB
Bit 0
The T3CNTRL register contains the following bits:
T3C3 Timer T3 mode control bit
T3C2 Timer T3 mode control bit
T3C1 Timer T3 mode control bit
T3C0
Timer T3 Start/Stop control in timer
modes 1 and 2, Timer T3 Underflow Interrupt
Pending Flag in timer mode 3
T3PNDA Timer T3 Interrupt Pending Flag (Autoreload
RA in mode 1, T3 Underflow in mode 2, T3A
capture edge in mode 3)
T3ENA Timer T3 Interrupt Enable for Timer Underflow
or T3A Input capture edge
T3PNDB Timer T3 Interrupt Pending Flag for T3B cap-
ture edge
T3ENB Timer T3 Interrupt Enable for T3B Input capture
edge
10.9.6 HSTCR Register (Address X'00AF)
T2IDLE
Bit 7
Reserved
T3HS
T2HS
Bit 0
The HSTCR register contains the following bits:
T2IDLE Allows T2 to run while in Idle Mode.
T3HS Places Timer T3 in High Speed Mode.
T2HS Places Timer T2 in High Speed Mode.
10.9.7 ITMR Register (Address X'00CF)
LSON HSON
Bit 7
DCEN
CCKS
EL
RSVD
ITSEL2 ITSEL1 ITSEL0
Bit 0
The ITMR register contains the following bits:
LSON Turns the low speed oscillator on or off.
HSON Turns the high speed oscillator on or off.
DCEN Selects the high speed oscillator or the low
speed oscillator as the Idle Timer Clock.
CCKSEL Selects the high speed oscillator or the low
speed oscillator as the primary CPU clock.
RSVD This bit is reserved and must be 0.
ITSEL2 Idle Timer period select bit.
ITSEL1 Idle Timer period select bit.
ITSEL0 Idle Timer period select bit.
10.9.8 ENAD Register (Address X'00CB)
ADCH3 ADCH2 ADCH1 ADCH0 ADMOD MUX
PSC ADBSY
Channel Select
Mode Mux Out Prescale Busy
Select
Bit 7
Bit 0
The ENAD register contains the following bits:
ADCH3 ADC channel select bit
ADCH2 ADC channel select bit
ADCH1 ADC channel select bit
ADCH0 ADC channel select bit
ADMOD Places the ADC in single-ended or differential
mode.
MUX Enables the ADC multiplexor output.
PSC
Switches the ADC clock between a divide by one
or a divide by sixteen of MCLK.
ADBSY Signifies that the ADC is currently busy perform-
ing a conversion. When set by the user, starts a
conversion.
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