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COP8AME9 Datasheet, PDF (12/83 Pages) National Semiconductor (TI) – 8-Bit CMOS Flash Microcontroller with 8k Memory, Dual Op Amps, Virtual EEROM, Temperature Sensor,10-Bit A/D and Brownout Reset
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AC Electrical Characteristics (−40˚C ≤ TA ≤ +85˚C) (Continued)
Note 3: Supply and IDLE currents are measured with CKI driven with a square wave Oscillator, CKO driven 180˚ out of phase with CKI, inputs connected to VCC
and outputs driven low but not connected to a load.
Note 4: The HALT mode will stop CKI from oscillating. Measurement of IDD HALT is done with device neither sourcing nor sinking current; with L, B, G0, and G2–G5
programmed as low outputs and not driving a load; all inputs tied to VCC; A/D converter and clock monitor and BOR disabled. Parameter refers to HALT mode
entered via setting bit 7 of the G Port data register.
Note 5: Pins G6 and RESET are designed with a high voltage input network. These pins allow input voltages > VCC and the pins will have sink current to VCC when
biased at voltages > VCC(the pins do not have source current when biased at a voltage below VCC). These two pins will not latch up. The voltage at these pins must
be limited to < (VCC+ 7V). WARNING: Voltages in excess of (VCC + 7V) will cause damage to these pins. This warning excludes ESD transients.
Note 6: If timer is in high speed mode, the minimum time is 1 MCLK. If timer is not in high speed mode, the minimum time is 1 tC.
Note 7: Absolute Maximum Ratings should not be exceeded.
Note 8: Vcc must be valid and stable before G6 is raised to a high voltage.
A/D Converter Electrical Characteristics (−20˚C ≤ TA ≤ +85˚C)
(Single-ended mode only)
Datasheet min/max specification limits are guaranteed by design, test, or statistical analysis.
Parameter
Conditions
Min
Typ
Max
Resolution
DNL
VCC = 5V
INL
VCC = 5V
Offset Error
VCC = 5V
Gain Error
VCC = 5V
Input Voltage Range
4.5V ≤ VCC ≤ 5.5V
0
Analog Input Leakage Current
10
±1
±2.5
±1.5
+0.5/-2.0
VCC
0.5
Analog Input Resistance (Note 9)
6k
Analog Input Capacitance
7
Conversion Clock Period
Conversion Time (Including S/H Time)
4.5V ≤ VCC ≤ 5.5V
0.8
30
15
Operating Current on AVCC
AVCC = 5.5V
Note 9: Resistance between the device input and the internal sample and hold capacitance.
0.2
0.6
Units
Bits
LSB
LSB
LSB
LSB
V
µA
Ω
pF
µs
A/D
Conversion
Clock
Cycles
mA
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