COP8AME9 Datasheet, PDF (15/83 Pages) National Semiconductor (TI) – 8-Bit CMOS Flash Microcontroller with 8k Memory, Dual Op Amps, Virtual EEROM, Temperature Sensor,10-Bit A/D and Brownout Reset

9.0 Pin Descriptions
The COP8AME9 I/O structure enables designers to recon-
figure the microcontroller’s I/O functions with a single in-
struction. Each individual I/O pin can be independently con-
figured as output pin low, output high, input with high
impedance or input with weak pull-up device. A typical ex-
ample is the use of I/O pins as the keyboard matrix input
lines. The input lines can be programmed with internal weak
pull-ups so that the input lines read logic high when the keys
are all open. With a key closure, the corresponding input line
will read a logic zero since the weak pull-up can easily be
overdriven. When the key is released, the internal weak
pull-up will pull the input line back to logic high. This elimi-
nates the need for external pull-up resistors. The high cur-
rent options are available for driving LEDs, motors and
speakers. This flexibility helps to ensure a cleaner design,
with less external components and lower costs. Below is the
general description of all available pins.
V_CC and GND are the power supply pins. All V_CC and GND
pins must be connected.
CKI is the clock input. This can be connected (in conjunction
with CKO) to an external crystal circuit to form a crystal
oscillator. See Oscillator Description section.
RESET is the master reset input. See Reset description
section.
AV_CC is the Analog Supply for A/D converter. It should be
connected to V_CC externally.
AGND is the ground pin for the A/D converter. It should be
connected to GND externally.
The device contains up to three bidirectional 8-bit I/O ports
(B, G and L) where each individual IO may be independently
configured as an input (Schmitt trigger inputs on ports L and
G), output or TRI-STATE under program control. Three data
memory address locations are allocated for each of these
I/O ports. Each I/O port has three associated 8-bit memory
mapped registers, the CONFIGURATION register, the output
DATA register and the Pin input register. (See the memory
map for the various addresses associated with the I/O ports.)
Figure 2 shows the I/O port configurations. The DATA and
CONFIGURATION registers allow for each port bit to be
individually configured under software control as shown be-
low:
CONFIGURATION
Register
0
0
1
1
DATA
Register
0
1
0
1
Port Set-Up
Hi-Z Input
(TRI-STATE Output)
Input with Weak Pull-Up
Push-Pull Zero Output
Push-Pull One Output
Port B is a 6-bit I/O port. All B pins have Schmitt triggers on
the inputs. The 28-pin packages do not have a full 8-bit port
and contain some unbonded, floating pads internally on the
chip. The binary value read from these bits is undetermined.
The application software should mask out these unknown
bits when reading the Port B register, or use only bit-access
program instructions when accessing Port B. These uncon-
nected bits draw power only when they are addressed (i.e.,
in brief spikes). Additionally, if Port B is being used with some
combination of digital inputs and analog inputs, the analog
inputs will read as undetermined values and should be
masked out by software.
Port B supports the analog inputs for the A/D converter. Port
B has the following alternate pin functions:
B7 Analog Channel 15 or A/D Input
B6 Analog Channel 14 or Analog Multiplexor Output
B5 Analog Channel 13 or AMP1 + Input
B4 Analog Channel 12 or AMP1 − Input
B3 Analog Channel 11 or AMP1 Output
B2 Analog Channel 10
Port G is an 8-bit port. Pin G0, G2–G5 are bi-directional I/O
ports. Pin G6 is always a general purpose Hi-Z input. All pins
have Schmitt Triggers on their inputs. Pin G1 serves as the
dedicated WATCHDOG output with weak pull-up if the
WATCHDOG feature is selected by the Option register.
The pin is a general purpose I/O if WATCHDOG feature is
not selected. If WATCHDOG feature is selected, bit 1 of the
Port G configuration and data register does not have any
effect on Pin G1 setup.
G7 serves as the dedicated output pin for the CKO clock
output.
There are two registers associated with the G Port, a data
register and a configuration register. Therefore, each of the 6
I/O bits (G0 - G5) can be individually configured under
software control.
Since G6 is an input only pin and G7 is the dedicated CKO
clock output pin, the associated bits in the data and configu-
ration registers for G6 and G7 are used for special purpose
functions as outlined below. Reading the G6 and G7 data
bits will return zeros.
The chip is placed in the HALT mode by writing a "1" to bit 7
of the Port G Data register. Similarly the chip will be placed
in the IDLE mode by writing a "1" to bit 6 of the Port G Data
Register.
Writing a “1” to bit 6 of the Port G Configuration Register
enables the MICROWIRE/PLUS to operate with the alter-
nate phase of the SK clock.
Config. Reg.
Data Reg.
G7
Not Used
HALT
G6
Alternate SK
IDLE
Port G has the following alternate features:
G7 CKO Oscillator dedicated output
G6 SI (MICROWIRE/PLUS Serial Data Input)
G5 SK (MICROWIRE/PLUS Serial Clock)
G4 SO (MICROWIRE/PLUS Serial Data Output)
G3 T1A (Timer T1 I/O)
G2 T1B (Timer T1 Capture Input)
G1 WDOUT WATCHDOG and/or Clock Monitor if WATCH-
DOG enabled, otherwise it is a general purpose I/O
G0 INTR (External Interrupt Input)
G0 through G3 are also used for In-System Emulation.
Port L is an 8-bit I/O port. All L-pins have Schmitt triggers on
the inputs.
Port L supports the Multi-Input Wake-Up feature on all eight
pins. Port L has the following alternate pin functions:
L7 Multi-Input Wake-up or T3B (Timer T3B Input)
L6 Multi-Input Wake-up or T3A (Timer T3A Input/Output)
L5 Multi-Input Wake-up or T2B (Timer T2B Input)
L4 Multi-Input Wake-up or T2A (Timer T2A Input/Output)
L3 Multi-Input Wake-up and/or RDX (USART Receive)
L2 Multi-Input Wake-up or TDX (USART Transmit)
L1 Multi-Input Wake-up and/or CKX (USART Clock) (Low
15
www.national.com