COP8AME9 Datasheet, PDF (68/83 Pages) National Semiconductor (TI) – 8-Bit CMOS Flash Microcontroller with 8k Memory, Dual Op Amps, Virtual EEROM, Temperature Sensor,10-Bit A/D and Brownout Reset

21.0 Memory Map
All RAM, ports and registers (except A and PC) are mapped
into data memory address space.
Address
S/ADD REG
0000 to 006F
0070 to 007F
xx80 to xx90
xx90 to xx9B
xx9C
xx9D
xx9E
xx9F
xxA0 to xxA3
xxA4
xxA5
xxA6
xxA7
xxA8
xxA9
xxAA
xxAB
xxAC to xxAE
xxAF
xxB0
xxB1
xxB2
xxB3
xxB4
xxB5
xxB6
xxB7
xxB8
xxB9
xxBA
xxBB
xxBC
Contents
On-Chip RAM bytes (112 bytes)
Unused RAM Address Space (Reads As
All Ones)
Unused RAM Address Space (Reads As
Undefined Data)
Reserved
Programmable Gain Amplifier Offset
Trim Register for N Channel Pair
(AMPTRMN)
Programmable Gain Amplifier Offset
Trim Register for P Channel Pair
(AMPTRMP)
Reserved
Reserved
Reserved
Port B Data Register
Port B Configuration Register
Port B Input Pins (Read Only)
Reserved for Port B
ISP Address Register Low Byte
(ISPADLO)
ISP Address Register High Byte
(ISPADHI)
ISP Read Data Register (ISPRD)
ISP Write Data Register (ISPWR)
Reserved
High Speed Timers Control Register
(HSTCR)
Timer T3 Lower Byte
Timer T3 Upper Byte
Timer T3 Autoload Register T3RA Lower
Byte
Timer T3 Autoload Register T3RA Upper
Byte
Timer T3 Autoload Register T3RB Lower
Byte
Timer T3 Autoload Register T3RB Upper
Byte
Timer T3 Control Register
Reserved
USART Transmit Buffer (TBUF)
USART Receive Buffer (RBUF)
USART Control and Status Register
(ENU)
USART Receive Control and Status
Register (ENUR)
USART Interrupt and Clock Source
Register (ENUI)
Address
S/ADD REG
xxBD
xxBE
xxBF
xxC0
xxC1
xxC2
xxC3
xxC4
xxC5
xxC6
xxC7
xxC8
xxC9
xxCA
xxCB
xxCC
xxCD
xxCE
xxCF
xxD0
xxD1
xxD2
xxD3
xxD4
xxD5
xxD6
xxD7 to xxDF
xxE0
xxE1
xxE2
xxE3 to xxE5
xxE6
xxE7
xxE8
xxE9
xxEA
xxEB
xxEC
Contents
USART Baud Register (BAUD)
USART Prescale Select Register (PSR)
Reserved
Timer T2 Lower Byte
Timer T2 Upper Byte
Timer T2 Autoload Register T2RA Lower
Byte
Timer T2 Autoload Register T2RA Upper
Byte
Timer T2 Autoload Register T2RB Lower
Byte
Timer T2 Autoload Register T2RB Upper
Byte
Timer T2 Control Register
WATCHDOG Service Register
(Reg:WDSVR)
MIWU Edge Select Register
(Reg:WKEDG)
MIWU Enable Register (Reg:WKEN)
MIWU Pending Register (Reg:WKPND)
A/D Converter Control Register (ENAD)
A/D Converter Result Register High Byte
(ADRSTH)
A/D Converter Result Register Low Byte
(ADRSTL)
A/D Amplifier Gain Register (ADGAIN)
Idle Timer Control Register (ITMR)
Port L Data Register
Port L Configuration Register
Port L Input Pins (Read Only)
Reserved
Port G Data Register
Port G Configuration Register
Port G Input Pins (Read Only)
Reserved
Reserved
E2 and Flash Memory Write Timing
Register (PGMTIM)
ISP Key Register (ISPKEY)
Reserved
Timer T1 Autoload Register T1RB Lower
Byte
Timer T1 Autoload Register T1RB Upper
Byte
ICNTRL Register
MICROWIRE/PLUS Shift Register
Timer T1 Lower Byte
Timer T1 Upper Byte
Timer T1 Autoload Register T1RA Lower
Byte
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