UPD98405 Datasheet, PDF (9/64 Pages) NEC – 155M ATM INTEGRATED SAR CONTROLLER

µPD98405
1. PIN FUNCTIONS
The package of the µPD98405 has 304 pins. For details on how to use each pin, refer to µPD98405 User’s
Manual (S12250E).
1.1 PHY Layer Device Interface Signal
The PHY Layer device interfaces include a UTOPIA interface by which the µPD98405 exchanges ATM cells with a
PHY device, and PHY control interface that is used to control a PHY device. The µPD98405 supports two types of
PHY layer device interfaces: UTOPIA octet and cell level. These modes are selected by setting the UOC bit of the
GMR register.
The PHY layer device interface signals are for an external PHY layer device. When using an internal PHY layer,
open all the pins except the common pins. Even when the internal PHY layer is used, an external receive FIFO can
be connected to the µPD98405 via the UTOPIA interface.
1.1.1 UTOPIA interface
Pin Name
Pin No.
I/O
I/O Level
Function
(1/2)
Rx7-Rx0
235-242
I
(Rx1 and
Rx0: Shared
with TFKC
and TFKT)
TTL
Receive data bus.
These pins constitute an 8-bit input bus that inputs receive data
from the network to the µPD98405 from the PHY layer device in
byte format. The µPD98405 reads the data on this bus in
synchronization with the rising edge of RCLK. Rx7 through Rx2
are internally pulled down.
Open the pins of this bus when they are not used. Pull up Rx1
when it is not used, and pull down Rx0 when it is not used.
RSOC
247
I
TTL
Receive cell start position.
This signal is input from the PHY layer device in synchronization
with the first byte of cell data. It is high while the first byte of a
header is input to Rx7 through Rx0.
This signal is internally pulled down.
RENBL_B
246
O
TTL
Receive enable.
This signal informs the PHY layer device that the µPD98405 is
ready to receive data in the next clock cycle.
Data Sheet S12689EJ2V0DS00
9