UPD98405 Datasheet, PDF (21/64 Pages) NEC – 155M ATM INTEGRATED SAR CONTROLLER

µPD98405
1.5 JTAG Boundary Scan Signals
Remark This function can be supported upon request.
These signals conform to IEEE1149.1 JTAG Boundary-Scan Standard.
Pin Name
JDI
JDO
JMS
JCK
JRST_B
Pin No.
285
284
283
282
281
I/O
I
O
3-state
I
I
I
I/O Level
TTL
TTL
TTL
TTL
TTL
Function
Boundary scan data input.
Connect this pin to ground when it is not used.
Boundary scan data output.
Open this pin when it is not used.
Boundary scan mode select.
Connect this pin to ground when it is not used.
Boundary scan clock input.
Connect this pin to ground when it is not used.
Boundary scan reset.
Connect this pin to ground when it is not used.
1.6 Other Signals
Pin Name
SCLK
Pin No.
198
PCI_MODE
118
TEST
271
I/O
I/O Level
Function
I
TTL
SAR system clock.
This pin supplies a clock for a SAR block operation.
The maximum clock frequency is 25 MHz.
I
TTL
PCI/generic bus mode.
This pin selects PCI or generic bus mode.
0: Generic bus mode
1: PCI bus mode
I
TTL
Internal test pin.
Open this pin. When a high level is input to this pin, the test
mode is selected.
This signal is internally pulled down.
The test mode is used for internal testing and cannot be used by
the user.
Data Sheet S12689EJ2V0DS00
21