UPD98405 Datasheet, PDF (12/64 Pages) NEC – 155M ATM INTEGRATED SAR CONTROLLER

µPD98405
1.2 Bus Interface Signals
The µPD98405 supports a PCI bus interface or generic bus interface. Whether the PCI bus interface or generic
bus interface is to be supported is selected by the PCI_MODE signal.
The PCI bus interface can be directly connected to a PCI bus. The generic bus interface can be connected to a
general I/O bus with a few circuits.
1.2.1 Generic bus interface signals (PCI_MODE pin: low level)
Pin Name
Pin No.
I/O
I/O Level
Function
(1/3)
AD31-AD0
295-297,
300-303,
3, 6, 9-12,
15-17,
34-36,
39-42,
45, 47, 48,
51-54,
57-58
I/O
3-state
TTL
Address/data.
These pins constitute a 32-bit address/data bus. They are
input/output pins multiplexing an address bus and a data bus.
An address is transferred at the first input/output clock. From
the second clock and onward, data is transferred. When the
µPD98405 is not accessing the bus, the AD bus goes into a
high-impedance state.
BE3_B
BE2_B
BE1_B
BE0_B
4
O
TTL
Byte enable.
18
3-state
These pins determine the byte that becomes valid in the master
33
cycle of the µPD98405. BE3_B corresponds to AD31 through
46
AD24, and BE0_B corresponds to AD7 through AD0. BE3_B
through BE0_B go into a high-impedance state when the
µPD98405 is not accessing a bus or when it is accessing a
slave.
PAR3
PAR2
PAR1
PAR0
66
I/O
TTL
Bus parity.
69
3-state
These pins indicate the parity of AD31 through AD0. A parity
70
check mode is set by the GMR register. Whether the parity is
71
enabled or disabled, whether an odd parity or even parity is
used, and whether a word parity or byte parity is used can be
specified. When byte parity is used, PAR3 indicates the parity
of AD31 through AD24, and PAR0 indicates the parity of AD7
through AD0. In the case of word parity, PAR2 through PAR0
do not function, and PAR3 serves as an input/output pin. These
pins function as output pins when an address is output and
when data is written, and as input pins when data is read.
When the µPD98405 is not accessing a bus, PAR3 through
PAR0 go into a high-impedance state. Pull up these pins when
they are not used.
OE_B
59
I
TTL
Output enable.
When this pin is low, the µPD98405 allows AD31 through AD0
and PAR3 through PAR0 to operate normally as three-state I/O
pins. These pins go into a high-impedance state while a high
level is input to this pin. Fix this pin to the low level in a system
where the above pins do not have to forcibly go into a high-
impedance state.
12
Data Sheet S12689EJ2V0DS00