UPD98405 Datasheet, PDF (56/64 Pages) NEC – 155M ATM INTEGRATED SAR CONTROLLER

µPD98405
PHY status access
Write
Parameter
SCLK ↑→ CA delay time
SCLK ↑→ PHRW_B delay time
SCLK ↑→ PHCE_B delay time
SCLK ↑→ CD delay time
PHCE_B ↑→ CD float time
Symbol
tDPCA
tDPHRW
tDPHCE
tDPCD
tFPCD
Condition
MIN.
1 tCYSCLK
– 10
TYP.
MAX.
20
20
20
23
1 tCYSCLK
+ 10
Unit
ns
ns
ns
ns *
ns
Write timing
SCLK
CA18-CA0
PHRW_B
PHCE_B
PHOE_B
CD31-CD0
1 clock
4 clocks
tDPCA
tDPHRW
tDPHCE
“H”
tDPCD
(Output)
1 clock
tDPCA
tDPHRW
tDPHCE
tFPCD
Read
Parameter
CD setup time
CD hold time
SCLK ↑→ CA delay time
SCLK ↑→ PHRW_B delay time
SCLK ↑→ PHCE_B delay time
SCLK ↑→ PHOE_B delay time
Symbol
tSPCD
tHPOECD
tDPCA
tDPHRW
tDPHCE
tDPHOE
Condition
MIN.
10
0
TYP.
MAX.
20
20
20
20
Unit
ns *
ns
ns
ns
ns
ns
56
Data Sheet S12689EJ2V0DS00