UPD98405 Datasheet, PDF (32/64 Pages) NEC – 155M ATM INTEGRATED SAR CONTROLLER

Bus master write
Parameter
CLK ↑→ FRAME_B, REQ64_B valid
time
CLK ↑→ FRAME_B, REQ64_B float
time
CLK ↑→ AD (Address) valid time
CLK ↑→ Data valid time
CLK ↑→ Data float time
CLK ↑→ PCBE_B valid time
CLK ↑→ PCBE_B float time
CLK ↑→IRDY_B valid time
CLK ↑→ IRDY_B float time
TRDY_B setup time
TRDY_B hold time
STOP_B setup time
STOP_B hold time
DEVSEL_B, ACK64_B setup time
DEVSEL_B, ACK64_B hold time
CLK ↑→ PAR valid time
CLK ↑→ PAR float time
PERR_B setup time
PERR_B hold time
Symbol
tDFRAME
tDFRAMEF
tDADDR
tDDATA
tDDATAF
tDPCBE
tDPCBEF
tDIRDY
tDIRDYF
tSTRDY
tHTRDY
tSSTOP
tHSTOP
tSDEVSEL
tHDEVSEL
tDPAR
tDPARF
tSPERR
tHPERR
Condition
µPD98405
MIN.
1
TYP.
MAX.
11
Unit
ns *
28
ns *
1
11
ns *
1
11
ns *
28
ns
1
11
ns *
28
ns
1
11
ns *
28
ns
8
ns *
1
ns *
8
ns *
1
ns *
8
ns *
1
ns *
1
11
ns *
28
ns
8
ns *
1
ns *
32
Data Sheet S12689EJ2V0DS00