UPD98405 Datasheet, PDF (19/64 Pages) NEC – 155M ATM INTEGRATED SAR CONTROLLER

µPD98405
1.3 Control Memory Interface Signals
The control memory interface is used by the µPD98405 to access the external control memory and external PHY
layer device. This interface consists of a 19-bit address bus, a 32-bit data bus. The control memory of the host
system can be accessed only through this interface.
Pin Name
CD31-CD0
CPAR3-
CPAR0
Pin No.
119-123,
126-130,
132-136,
139-144,
146-150,
155-159, 161
162-165
I/O
I/O 3-state
I/O
CA18-CA0 166, 168-173,
O
176-181,
183-188
CWE_B
195
O
COE_B
196
O
CBE3_B-
191-194
O
CBE0_B
INITD
197
I
I/O Level
TTL
Function
Control memory data.
These three-state I/O pins constitute a 32-bit data bus that is
used to transfer data to and from the control memory or PHY
layer device.
These signals are internally pulled down.
TTL
Control memory parity.
These signals indicate the parity of CD31 through CD0 every 8
bits. In the read cycle, the µPD98405 checks the parity (when
enabled). In the write cycle, it outputs the parity.
These signals are internally pulled down.
TTL
Control memory address.
These signals constitute a 19-bit address bus that outputs an
address to the control memory or PHY layer device during a
read/write operation.
TTL
Control memory write enable.
This signal indicates the direction in which the control memory
is accessed.
1: Read access
0: Write access
TTL
Control memory output enable.
This signal enables or disables data output of the control
memory.
TTL
Local port byte enable.
These signals indicate the byte of the control port to be read or
written.
TTL
Initialization disable.
This signal is used to disable automatic initialization of the
control memory during chip test. Directly connect INITD to GND
during normal operation other than test.
Data Sheet S12689EJ2V0DS00
19