UPD98405 Datasheet, PDF (53/64 Pages) NEC – 155M ATM INTEGRATED SAR CONTROLLER

Control memory access
Write
Parameter
CA → CWE_B ↓ setup time
CBE_B → CWE_B ↓ setup time
CWE_B low-level width
CWE_B ↑→ CD float time
CWE_B ↑→ COE_B delay time
CA hold time (vs CWE_B ↑)
CBE_B hold time (vs CWE_B ↑)
CD output time (vs CWE_B ↑)
CWE_B ↑→ CPAR float time
CPAR output time (vs CWE_B ↑)
Symbol
tSCWE
tSCWE2
tCWEL
tFCD
tDCOE
tHCA
tHCBE
tSCD
tFCPAR
tSCPAR
Write timing
SCLK
µPD98405
Condition
MIN.
0
0
1 tSCLKL – 2
0
TYP.
0
0
0
15
0
15
MAX.
1 tSCLKL
+ 8.59
1 tSCLKL
+ 8.65
Unit
ns
ns
ns
ns *
ns
ns
ns
ns *
ns *
ns *
CBE3_B-
CBE0_B
CA18-CA0
CWE_B
COE_B
CD31-CD0
CPAR3-CPAR0
tSCWE2
tSCWE
tHCBE
tCWEL
tHCA
tDCOE
tSCD
(Output)
tSCPAR
(Output)
tFCD
tFCPAR
Data Sheet S12689EJ2V0DS00
53