UPD98405 Datasheet, PDF (30/64 Pages) NEC – 155M ATM INTEGRATED SAR CONTROLLER

PCI Bus Interface
Bus master read
Parameter
CLK ↑→ FRAME_B, REQ64_B valid
time
CLK ↑→ FRAME_B, REQ64_B float
time
CLK ↑→ AD (Address) valid time
CLK ↑→ AD (Address) float time
AD (Data) setup time
AD (Data) hold time
CLK ↑→ PCBE_B valid time
CLK ↑→ PCBE_B float time
CLK ↑→IRDY_B valid time
CLK ↑→ IRDY_B float time
TRDY_B setup time
TRDY_B hold time
DEVSEL_B, ACK64_B setup time
DEVSEL_B, ACK64_B hold time
STOP_B setup time
STOP_B hold time
CLK ↑→ PAR valid time
CLK ↑→ PAR float time
PAR setup time
PAR hold time
CLK ↑→ PERR_B valid time
CLK ↑ → PERR_B float time
Symbol
tDFRAME
tDFRAMEF
tDADDR
tDADDRF
tSDATA
tHDATA
tDPCBE
tDPCBEF
tDIRDY
tDIRDYF
tSTRDY
tHTRDY
tSDEVSEL
tHDEVSEL
tSSTOP
tHSTOP
tDPAR
tDPARF
tSPAR
tHPAR
tDPERR
tDPERRF
Condition
µPD98405
MIN.
1
TYP.
MAX.
11
Unit
ns *
28
ns *
1
11
ns *
28
ns
8
ns *
1
ns *
1
11
ns *
28
ns
1
11
ns *
28
ns *
8
ns *
1
ns *
8
ns *
1
ns *
8
ns *
1
ns *
1
11
ns *
28
ns
8
ns *
1
ns *
1
11
ns *
28
ns
30
Data Sheet S12689EJ2V0DS00