UPD98405 Datasheet, PDF (15/64 Pages) NEC – 155M ATM INTEGRATED SAR CONTROLLER

µPD98405
1.2.2 PCI bus interface signal (PCI_MODE pin: high level)
The µPD98405 has a 32-/64-bit PCI bus interface. This bus interface can be directly connected to a PCI bus. In
addition, the µPD98405 also has a serial EEPROM interface and an expansion ROM interface.
<1> PCI bus interface signals
Pin Name
AD31-AD0
PCBE3_B
PCBE2_B
PCBE1_B
PCBE0_B
Pin No.
295-297,
300-303,
3, 6, 9-12,
15-17,
34-36,
39-42,
45, 47, 48,
51-54,
57-58
4
18
33
46
I/O
I/O
3-state
I/O
3-state
PAR
30
I/O
3-state
FRAME_B
21
I/O
Sustained
3-state
TRDY_B
IRDY_B
23
I/O
Sustained
3-state
22
I/O
Sustained
3-state
I/O Level
PCI
Function
(1/2)
Address/data.
AD31 through AD0 constitute a 32-bit multiplexed address/data
bus. When the µPD98405 operates as a bus master, it drives
an address at the first clock and transfers data at the second
clock and onward.
PCI
Bus command/byte enable.
These signals define a “bus command” (bus transaction that
occurs) in the address phase. In the data phase, they indicate
which byte lane holds valid data. The PCBE3_B pin
corresponds to byte 3 (bits 31 through 24), and PCBE0_B pin
corresponds to byte 0 (bits 7 through 0).
PCI
Parity.
This signal indicates an even parity on the AD31 through AD0
and PCBE3_B through PCBE0_B pins, including the PAR
signal. When the µPD98405 is operating as a master, the PAR
signal becomes active in the address and write data phases.
When the µPD98405 is operating as a target, this signal
becomes active in the read data phase.
PCI
Frame.
This signal indicates the start and period of a bus transaction.
When this signal is asserted active, it indicates the start of a bus
transaction. While it is active, data is transferred. It is
deasserted inactive when the next data transfer phase will
transfer last data of the transaction.
PCI
Target ready.
This signal goes low when the target device is ready to
complete the transaction of the current data. This signal is used
in combination with IRDY_B, and read/write data transfer is
executed when both IRDY_B and TRDY_B signals are low.
PCI
Initiator ready.
This signal goes low when the initiator is ready to complete the
transaction of the current data. This signal is used in
combination with TRDY_B, and read/write data transfer is
executed when both IRDY_B and TRDY_B are low.
If FRAME_B and IRDY_B are both inactive, the bus cycle is not
executed. A wait cycle is inserted until both IRDY_B and
TRDY_B are asserted active.
Data Sheet S12689EJ2V0DS00
15