UPD98405 Datasheet, PDF (28/64 Pages) NEC – 155M ATM INTEGRATED SAR CONTROLLER

µPD98405
AC Characteristics (TA = 0 to +70°C, VDD = +3.3 V ± 0.3 V, output pin load: 30 pF)
CLK input (BUS interface clock - CLK pin)
Parameter
CLK cycle time
CLK high-level width
CLK low-level width
CLK slew rate
Symbol
tCYCLK
tCLKH
tCLKL
slewCLK
Condition
MIN.
30
11
11
1
TYP.
MAX.
125
4
Unit
ns
ns
ns
V/ns
2.0 V
CLK
1.5 V
0.8 V
tCLKH
tCYCLK
tCLKL
2.4 V (MIN.)
0.4 V (MAX.)
SCLK input (internal system clock - SCLK pin)
Parameter
SCLK cycle time
SCLK high-level width
SCLK low-level width
SCLK slew rate
Symbol
tCYSCLK
tSCLKH
tSCLKL
slewSCLK
Condition
MIN.
40
15
15
1
TYP.
MAX.
125
4
Unit
ns
ns
ns
V/ns
2.0 V
SCLK
1.5 V
0.8 V
tSCLKH
tCYSCLK
tSCLKL
2.4 V (MIN.)
0.4 V (MAX.)
RST input
Parameter
RST low-level width
RST slew rate
Symbol
tRSTL
slewRST
Condition
MIN.
tCYCLK
50
TYP.
MAX.
Unit
ns
V/ns
28
Data Sheet S12689EJ2V0DS00