UPD98405 Datasheet, PDF (11/64 Pages) NEC – 155M ATM INTEGRATED SAR CONTROLLER

µPD98405
1.1.2 PHY device control interface (external PHY mode, PHM of GMR register = 1)
Pin Name
PHR/W_B
(shared with
PHYALM)
Pin No.
266
PHOE_B
265
PHCE_B
267
(shared with
SD)
PHINT_B
268
(shared with
REFCLK)
PHRST_B
264
I/O
I/O Level
Function
O
TTL
PHY read/write.
The µPD98405 indicates the PHY layer device control direction
by using this pin.
1: Read
0: Write
O
TTL
PHY layer output enable.
The µPD98405 enables output by the PHY layer device by
making this signal low.
O
TTL
PHY layer chip enable.
The µPD98405 makes this signal low when it accesses the PHY
layer device.
I
TTL
PHY layer interrupt.
This pin inputs an interrupt signal to the µPD98405 from the
PHY layer device. The PHY layer device informs the µPD98405
that it has an interrupt source by inputting a low level to this pin.
Pull up this pin when it is not used.
O
TTL
PHY layer reset.
This signal is used to reset the PHY layer device. The
µPD98405 keeps this pin low for the duration of 17 clock cycles
when a low level is input to the RST_B pin or when software
reset is executed.
Caution The PHCE_B/SD pins are multiplexed pins and their functions differ depending on whether the
internal PHY mode or external PHY mode is selected (by using the PHM bit of the GMR register).
Because the PHCE_B/SD pins change the mode between input and output depending on the
selected mode, be sure to correctly set the PHM bit of the GMR register.
Data Sheet S12689EJ2V0DS00
11