UPD98405 Datasheet, PDF(5/64 Page) NEC – 155M ATM INTEGRATED SAR CONTROLLER

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UPD98405 Datasheet, PDF (5/64 Pages) NEC – 155M ATM INTEGRATED SAR CONTROLLER

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ÂµPD98405

PIN NAME

ABRT_B

: Abort

ACK64_B

: Acknowledge 64-bit Transfer

AD63-AD0

: Address/Data

AGND

: Ground for Analog Part

ASEL_B

: Slave Address Select

ATTN_B

: Attention

AVDD3

: +3.3 V Power Supply for

Analog Part

BE3_B-BE0_B

: Byte Enable

CA18-CA0

: Control Memory Address

CBE3_B-CBE0_B : Local Port Byte Enable

CD31-CD0

: Control Memory Data

CLK

: Clock

COE_B

: Control Memory Output Enable

CPAR3-CPAR0 : Control Memory parity

CWE_B

: Control Memory Write Enable

DEVSEL_B

: Device Select

DR/W_B

: DMA Read/Write

EMPTY_B/RCLAV : PHY Empty/Rx Cell Available

ERR_B

: Error

E2PCLK

: Clock for EEPROM

E2PCS

: EEPROM Chip Select

E2PDI

: Serial Data Input from EEPROM

E2PDO

: Serial Data Output to EEPROM

FRAME_B

: Cycle Frame

FULL_B/TCLAV : PHY Buffer full/Tx Cell Available

GND

: Ground for Digital Part

GNT_B

: Grant

HGND

: Ground for High-Speed Part

HVDD3

: +3.3 V Power Supply for

High-Speed Part

IDSEL

: ID Select

INITD

: Initialization Disable

INTR_B

: Interrupt

IRDY_B

: Initiator Ready

JCK

: JTAG Test Pin

JDI

: JTAG Test Pin

JDO

: JTAG Test Pin

JMS

: JTAG Test Pin

JRST_B

: JTAG Test Pin

OE_B

: Output Enable

PAR

: Parity

PAR3-PAR0

: Bus Party

PAR64

: Parity 64 bits

PCBE7_B-PCBE0_B: Bus Command and Byte Enables

PCI_MODE

: PCI Mode

PERR_B

: Parity Error

PHCE_B

: PHY Chip Enable

PHINT_B

: PHY Interrupt

PHOE_B

: PHY Output Enable

PHRST_B

: PHY Reset

PHR/W_B

: PHY Read/Write

PHYALM

: Physical Alarm

RCLK

: Receive Clock

RCIC

: Receive Clock Input Complement

RCIT

: Receive Clock Input True

RDIC

: Receive Data Input Complement

RDIT

: Receive Data Input True

PDY_B

: Target Ready

REFCLK

: Reference Clock

RENBL_B

: Receive Enable

REQ64_B

: Request 64-bit Transfer

REQ_B

: Request

RGND

: Ground for Receive PLL Part

ROMA15-ROMA0: Expansion ROM Address

ROMCS_B

: Expansion ROM Chip Select

ROMD7-ROMD0 : Expansion ROM Input Data

ROMOE_B

: Expansion ROM Output Enable

RSOC

: Receive Start Cell

RST_B

: Reset

RVDD3

: +3.3 V Power Supply for Receive

PLL Part

Rx7-Rx0

: Receive Data Bus

SCLK

: SAR System Clock

SD

: Signal Detect

SEL_B

: Slave Select

SERR_B

: System Error

SIZE2-SIZE0 : Burst Size

SR/W_B

: Slave Read /Write

STOP_B

: Stop

TCLK

: Transmit Clock

TDOC

: Transmit Data Output Complement

TDOT

: Transmit Data Output True

TENBL_B

: Transmit Enable

TEST

: Test Mode Pin

TFKC

: Transmit Reference Clock Complement

TFKT

: Transmit Reference Clock True

TRDY_B

: Target Ready

TSOC

: Transmit Start of Cell

Tx7-Tx0

: Transmit Data Bus

VDD3

: +3.3 V Power Supply for Digital Part

VDD5

: +5 V Power Supply for Digital Part

Data Sheet S12689EJ2V0DS00

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