MT40A1G4HX-093E Datasheet, PDF (82/365 Pages) Micron Technology – 4Gb: x4, x8, x16 DDR4 SDRAM

4Gb: x4, x8, x16 DDR4 SDRAM
Command Address Latency
When the CAL mode is enabled or being enabled, the earliest the next MRS command
can be issued is ^tMRD_CAL is equal to ^tMOD + ^tCAL. The two following figures are ex-
amples.
Figure 27: CAL Enabling MRS to Next MRS Command, ^tMRD_CAL
T0
CK_c
CK_t
T1
Ta0
Ta1
Ta2
Ta3
Ta4
Tb0
Tb1
Tb2
Tb3
Command
Valid
Address
Valid
MRS
Valid
DES
Valid
DES
Valid
DES
Valid
DES
Valid
DES
Valid
DES
t_CAL
Valid
DES
Valid
MRS
Valid
DES
Valid
CS_n
Settings Old settings
t_{MRD_CAL}
Updating settings
Note: 1. Command address latency mode is enabled at T1.
Updating settings
Time Break
Don’t Care
Figure 28: ^tMRD_CAL, Mode Register Cycle Time With CAL Enabled
7
CK_c
CK_t
7
7D
7D
7D
7E
7E
7E
7F
7F
7F
Command
Address
9DOLG
W _&$/
'(6
9DOLG
9DOLG
'(6
9DOLG
056
9DOLG
'(6
9DOLG
'(6
9DOLG
'(6
W _&$/
'(6
9DOLG
9DOLG
'(6
9DOLG
056
9DOLG
'(6
9DOLG
CS_n
Settings
2OGVHWWLQJV
W _05'B&$/
8SGDWLQJVHWWLQJV
1HZVHWWLQJV
7LPH%UHDN
'RQ¶W&DUH
Note: 1. MRS at Ta1 may or may not modify CAL, ^tMRD_CAL is computed based on new ^tCAL set-
ting if modified.
CAL Examples: Consecutive READ BL8 with two different CALs and 1^tCK preamble in
different bank group shown in the following figures.
09005aef84af6dd0
4gb_ddr4_dram.pdf - Rev. G 1/17 EN
82
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