MT40A1G4HX-093E Datasheet, PDF (135/365 Pages) Micron Technology – 4Gb: x4, x8, x16 DDR4 SDRAM

4Gb: x4, x8, x16 DDR4 SDRAM
Post Package Repair
d. JEDEC allows A6:0 to be "Don't Care" on 4Gb and 8Gb devices from a suppli-
er perspective and the user should rely on vendor datasheet.
Table 43: PPR MR0 Guard Key Settings
MR0
First guard key
Second guard key
Third Guard key
Fourth guard key
BG1:0 BA1:0 A17:12 A11
A10
A9
A8
A7
A6:0
0
0
xxxxxx
1
1
0
0
1
1111111
0
0
xxxxxx
0
1
1
1
1
1111111
0
0
xxxxxx
1
0
1
1
1
1111111
0
0
xxxxxx
0
0
1
1
1
1111111
3. After ^tMOD, issue an ACT command with failing BG and BA with the row address
to be repaired.
4. After ^tRCD, issue a WR command with BG and BA of failing row address.
a. The address must be at valid levels, but the address is a "Don't Care."
5. All DQ of the target DRAM should be driven LOW for 4nCK (bit 0 through bit 7)
after WL (WL = CWL + AL + PL) in order for sPPR to initiate repair.
a. Repair will be initiated to the target DRAM only if all DQ during bit 0 through
bit 7 are LOW.
b. Repair will not be initiated to the target DRAM if any DQ during bit 0 through
bit 7 is HIGH.
1. JEDEC states: All DQs of target DRAM should be LOW for 4^tCK. If HIGH
is driven to all DQs of a DRAM consecutively for equal to or longer than
the first 2^tCK, then DRAM does not conduct hPPR and retains data if
REF command is properly issued; if all DQs are neither LOW for 4^tCK
nor HIGH for equal to or longer than the first 2^tCK, then hPPR mode ex-
ecution is unknown.
c. DQS should function normally.
6. REF command may NOT be issued at anytime while in sPPR mode.
7. Issue PRE after ^tWR time so that the device can repair the target row during ^tWR
time.
a. Wait ^tPGM_Exit_s after PRE to allow the device to recognize the repaired tar-
get row address.
8. Issue MR4[5] 0 command to sPPR mode disable.
a. Wait ^tPGMPST_s for sPPR mode exit to complete.
b. After ^tPGMPST_s has expired, any valid command may be issued.
The entire sequence from sPPR mode enable through sPPR mode disable may be repea-
ted if more than one repair is to be done.
After sPPR mode has been exited, the DRAM controller can confirm if the target row
was repaired correctly by writing data into the target row and reading it back.
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4gb_ddr4_dram.pdf - Rev. G 1/17 EN
135
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