MT40A1G4HX-093E Datasheet, PDF (247/365 Pages) Micron Technology – 4Gb: x4, x8, x16 DDR4 SDRAM

4Gb: x4, x8, x16 DDR4 SDRAM
WRITE Operation
Figure 197: WRITE (BL8/BC4-OTF/Fixed) with 1^tCK Preamble and Write CRC in Same or Different Bank
Group
T0
T1
T2
T6
T7
T8
T9
T10
T11
T12
T13
T14
T15
T16
T17
T18
T19
T20
CK_c
CK_t
Command WRITE
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
t_{WR_CRC_DM}
4 Clocks
t_{WTR_S_CRC_DM/}t_{WTR_L_CRC_DM}
Bank Group
BGa
Address
Address
Bank
Col n
DQS_t,
DQS_c
DQ x4,
BL = 8
t_WPRE
t_WPST
WL = AL + CWL = 9
DI
n
DI DI DI DI DI DI DI
n+1 n+2 n+3 n+4 n+5 n+6 n+7
CRC
CRC
DQ x8/X16,
BL = 8
DMx4/x8/x16
BL = 8
DQ x4,
BC = 4 (OTF/Fixed)
DI
n
DI DI DI DI DI DI DI
n+1 n+2 n+3 n+4 n+5 n+6 n+7
CRC
DM DM DM DM DM DM DM DM
n n+1 n+2 n+3 n+4 n+5 n+6 n+7
DI DI DI DI
n n+1 n+2 n+3
CRC CRC
DQ x8/X16,
BC = 4 (OTF/Fixed)
DI DI DI DI
n n+1 n+2 n+3
CRC
DM x4/x8/x16
BC = 4 (OTF / Fixed)
DM DM DM DM
n n+1 n+2 n+3
Time Break
Transitioning Data
Don’t Care
Notes:
1. BL8/BC4, AL = 0, CWL = 9, Preamble = 1^tCK.
2. DI n (or b) = data-in from column n (or column b).
3. DES commands are shown for ease of illustration; other commands may be valid at
these times.
4. BL8 setting activated by either MR0[1:0] = 00 or MR0[1:0] = 01 and A12 = 1 during
WRITE command at T0.
5. BC4 setting activated by either MR0[1:0] = 10 or MR0[1:0] = 01 and A12 = 0 during
WRITE command at T0.
6. CA parity = Disable, CS to CA latency = Disable, Read DBI = Disable, Write CRC = Enable,
DM = Enable.
7. The write recovery time (^tWR_CRC_DM) and write timing parameter (^tWTR_S_CRC_DM/
t_{WTR_L_CRC_DM) are referenced from the first rising clock edge after the last write da-}
ta shown at T13.
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4gb_ddr4_dram.pdf - Rev. G 1/17 EN
247
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