MT40A1G4HX-093E Datasheet, PDF (45/365 Pages) Micron Technology – 4Gb: x4, x8, x16 DDR4 SDRAM

4Gb: x4, x8, x16 DDR4 SDRAM
Mode Register 0
Burst Length, Type, and Order
Accesses within a given burst may be programmed to sequential or interleaved order.
The ordering of accesses within a burst is determined by the burst length, burst type,
and the starting column address as shown in the following table. Burst length options
include fixed BC4, fixed BL8, and on-the-fly (OTF), which allows BC4 or BL8 to be selec-
ted coincidentally with the registration of a READ or WRITE command via A12/BC_n.
Table 8: Burst Type and Burst Order
Note 1 applies to the entire table
Starting
Burst
Length
READ/ Column Address
WRITE
(A[2, 1, 0])
BC4
READ
000
001
010
011
100
101
110
111
WRITE
0, V, V
1, V, V
BL8
READ
000
001
010
011
100
101
110
111
WRITE
V, V, V
Burst Type = Sequential
(Decimal)
0, 1, 2, 3, T, T, T, T
1, 2, 3, 0, T, T, T, T
2, 3, 0, 1, T, T, T, T
3, 0, 1, 2, T, T, T, T
4, 5, 6, 7, T, T, T, T
5, 6, 7, 4, T, T, T, T
6, 7, 4, 5, T, T, T, T
7, 4, 5, 6, T, T, T, T
0, 1, 2, 3, X, X, X, X
4, 5, 6, 7, X, X, X, X
0, 1, 2, 3, 4, 5, 6, 7
1, 2, 3, 0, 5, 6, 7, 4
2, 3, 0, 1, 6, 7, 4, 5
3, 0, 1, 2, 7, 4, 5, 6
4, 5, 6, 7, 0, 1, 2, 3
5, 6, 7, 4, 1, 2, 3, 0
6, 7, 4, 5, 2, 3, 0, 1
7, 4, 5, 6, 3, 0, 1, 2
0, 1, 2, 3, 4, 5, 6, 7
Burst Type = Interleaved
(Decimal)
0, 1, 2, 3, T, T, T, T
1, 0, 3, 2, T, T, T, T
2, 3, 0, 1, T, T, T, T
3, 2, 1, 0, T, T, T, T
4, 5, 6, 7, T, T, T, T
5, 4, 7, 6, T, T, T, T
6, 7, 4, 5, T, T, T, T
7, 6, 5, 4, T, T, T, T
0, 1, 2, 3, X, X, X, X
4, 5, 6, 7, X, X, X, X
0, 1, 2, 3, 4, 5, 6, 7
1, 0, 3, 2, 5, 4, 7, 6
2, 3, 0, 1, 6, 7, 4, 5
3, 2, 1, 0, 7, 6, 5, 4
4, 5, 6, 7, 0, 1, 2, 3
5, 4, 7, 6, 1, 0, 3, 2
6, 7, 4, 5, 2, 3, 0, 1
7, 6, 5, 4, 3, 2, 1, 0
0, 1, 2, 3, 4, 5, 6, 7
Notes
2, 3
2, 3
2, 3
2, 3
2, 3
2, 3
2, 3
2, 3
2, 3
2, 3
3
Notes:
1. 0...7 bit number is the value of CA[2:0] that causes this bit to be the first read during a
burst.
2. When setting burst length to BC4 (fixed) in MR0, the internal WRITE operation starts
two clock cycles earlier than for the BL8 mode, meaning the starting point for ^tWR and
t_{WTR will be pulled in by two clocks. When setting burst length to OTF in MR0, the in-}
ternal WRITE operation starts at the same time as a BL8 (even if BC4 was selected during
column time using A12/BC4_n) meaning that if the OTF MR0 setting is used, the starting
point for ^tWR and ^tWTR will not be pulled in by two clocks as described in the BC4
(fixed) case.
3. T = Output driver for data and strobes are in High-Z.
V = Valid logic level (0 or 1), but respective buffer input ignores level on input pins.
X = “Don’t Care.”
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4gb_ddr4_dram.pdf - Rev. G 1/17 EN
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