MT40A1G4HX-093E Datasheet, PDF (80/365 Pages) Micron Technology – 4Gb: x4, x8, x16 DDR4 SDRAM

4Gb: x4, x8, x16 DDR4 SDRAM
Command Address Latency
Command Address Latency
DDR4 supports the command address latency (CAL) function as a power savings fea-
ture. This feature can be enabled or disabled via the MRS setting. CAL timing is defined
as the delay in clock cycles (^tCAL) between a CS_n registered LOW and its correspond-
ing registered command and address. The value of CAL in clocks must be programmed
into the mode register (see MR1 Register Definition table) and is based on the equation
t_CK(ns)/t_{CAL(ns), rounded up in clocks.}
Figure 23: CAL Timing Definition
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15
CLK
CS_n
CMD/ADDR
t_CAL
CAL gives the DRAM time to enable the command and address receivers before a com-
mand is issued. After the command and the address are latched, the receivers can be
disabled if CS_n returns to HIGH. For consecutive commands, the DRAM will keep the
command and address input receivers enabled for the duration of the command se-
quence.
Figure 24: CAL Timing Example (Consecutive CS_n = LOW)
1
2
3
4
5
6
7
8
9 10 11 12
CLK
CS_n
CMD/ADDR
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4gb_ddr4_dram.pdf - Rev. G 1/17 EN
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