MT40A1G4HX-093E Datasheet, PDF (256/365 Pages) Micron Technology – 4Gb: x4, x8, x16 DDR4 SDRAM

4Gb: x4, x8, x16 DDR4 SDRAM
Dynamic ODT
Dynamic ODT
In certain application cases and to further enhance signal integrity on the data bus, it is
desirable that the termination strength of the device can be changed without issuing an
MRS command. This requirement is supported by the dynamic ODT feature.
Functional Description
Dynamic ODT mode is enabled if bit A9 or A10 of MR2 is set to 1.
• Three R_TT values are available: R_TT(NOM), R_TT(WR), and R_TT(Park).
– The value for R_TT(NOM) is preselected via bits MR1[10:8].
– The value for R_TT(WR) is preselected via bits MR2[11:9].
– The value for R_TT(Park) is preselected via bits MR5[8:6].
• During operation without WRITE commands, the termination is controlled as fol-
lows:
– Nominal termination strength R_TT(NOM) or R_TT(Park) is selected.
– R_TT(NOM) on/off timing is controlled via ODT pin and latencies DODTLon and
DODTLoff, and R_TT(Park) is on when ODT is LOW.
• When a WRITE command (WR, WRA, WRS4, WRS8, WRAS4, and WRAS8) is regis-
tered, and if dynamic ODT is enabled, the termination is controlled as follows:
– Latency ODTLcnw after the WRITE command, termination strength R_TT(WR) is se-
lected.
– Latency ODTLcwn8 (for BL8, fixed by MRS or selected OTF) or ODTLcwn4 (for
BC4, fixed by MRS or selected OTF) after the WRITE command, termination
strength R_TT(WR) is de-selected.
One or two clocks will be added into or subtracted from ODTLcwn8 and ODTLcwn4,
depending on write CRC mode and/or 2^tCK preamble enablement.
The following table shows latencies and timing parameters relevant to the on-die termi-
nation control in dynamic ODT mode. The dynamic ODT feature is not supported in
DLL-off mode. An MRS command must be used to set R_TT(WR) to disable dynamic ODT
externally (MR2[11:9] = 000).
Table 74: Dynamic ODT Latencies and Timing (1^tCK Preamble Mode and CRC Disabled)
Name and Description
ODT latency for change from
R_TT(Park)/R_TT(NOM) to R_TT(WR)
ODT latency for change from
R_TT(WR) to R_TT(Park)/R_TT(NOM) (BC =
4)
ODT latency for change from
R_TT(WR) to R_TT(Park)/R_TT(NOM) (BL =
8)
R_TT change skew
Abbr.
ODTLcnw
ODTLcwn
4
ODTLcwn
8
t_ADC
Defined from
Defined to
Registering external Change R_TT strength
WRITE command from R_TT(Park)/R_TT(NOM)
to R_TT(WR)
Registering external
WRITE command
Registering external
WRITE command
Change R_TT strength
from R_TT(WR) to
R_TT(Park)/R_TT(NOM)
Change R_TT strength
from R_TT(NOM) to
R_TT(WR)
ODTLcnw
ODTLcwn
R_TT valid
Definition for All
DDR4 Speed Bins
ODTLcnw = WL - 2
ODTLcwn4 = 4 +
ODTLcnw
ODTLcwn8 = 6 +
ODTLcnw
t_{ADC (MIN) = 0.3}
t_{ADC (MAX) = 0.7}
Unit
t_CK
t_CK
t_CK
(AVG)
t_CK
(AVG)
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4gb_ddr4_dram.pdf - Rev. G 1/17 EN
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