MT40A1G4HX-093E Datasheet, PDF (111/365 Pages) Micron Technology – 4Gb: x4, x8, x16 DDR4 SDRAM

4Gb: x4, x8, x16 DDR4 SDRAM
Command/Address Parity
4. Command execution is unknown; the corresponding DRAM internal state change may
or may not occur. The DRAM controller should consider both cases and make sure that
the command sequence meets the specifications.
5. Only a DESELECT command is allowed; CKE may go HIGH prior to Td2 as long as DES
commands are issued.
Figure 54: Parity Entry Timing Example – ^tMRD_PAR
Ta0
Ta1
Ta2
Tb0
Tb1
Tb2
CK_c
CK_t
Command
DES
MRS
DES
DES
MRS
DES
Parity latency
PL = 0
Updating setting
t_{MRD_PAR}
PL = N
Enable
parity
Time Break
Don’t Care
Note: 1. ^tMRD_PAR = ^tMOD + N; where N is the programmed parity latency.
Figure 55: Parity Entry Timing Example – ^tMOD_PAR
Ta0
Ta1
Ta2
Tb0
Tb1
Tb2
CK_c
CK_t
Command
DES
MRS
DES
DES
Valid
DES
Parity latency
PL = 0
Updating setting
t_{MOD_PAR}
PL = N
Enable
parity
Time Break
Don’t Care
Note: 1. ^tMOD_PAR = ^tMOD + N; where N is the programmed parity latency.
Figure 56: Parity Exit Timing Example – ^tMRD_PAR
Ta0
CK_c
CK_t
Ta1
Ta2
Tb0
Tb1
Tb2
Command
DES
MRS
DES
DES
MRS
DES
Parity latency
PL = N
Updating setting
t_{MRD_PAR}
Disable
parity
Time Break
Don’t Care
Note: 1. ^tMRD_PAR = ^tMOD + N; where N is the programmed parity latency.
09005aef84af6dd0
4gb_ddr4_dram.pdf - Rev. G 1/17 EN
111
Micron Technology, Inc. reserves the right to change products or specifications without notice.
‹ 2014 Micron Technology, Inc. All rights reserved.