MT40A1G4HX-093E Datasheet, PDF(15/365 Page) Micron Technology – 4Gb: x4, x8, x16 DDR4 SDRAM

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MT40A1G4HX-093E Datasheet, PDF (15/365 Pages) Micron Technology – 4Gb: x4, x8, x16 DDR4 SDRAM

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4Gb: x4, x8, x16 DDR4 SDRAM

Features

List of Tables

Table 1: Key Timing Parameters ....................................................................................................................... 2

Table 2: Addressing ......................................................................................................................................... 2

Table 3: Ball Descriptions .............................................................................................................................. 25

Table 4: State Diagram Command Definitions ................................................................................................ 33

Table 5: Supply Power-up Slew Rate ............................................................................................................... 35

Table 6: Address Pin Mapping ........................................................................................................................ 43

Table 7: MR0 Register Definition .................................................................................................................... 43

Table 8: Burst Type and Burst Order ............................................................................................................... 45

Table 9: Address Pin Mapping ........................................................................................................................ 47

Table 10: MR1 Register Definition .................................................................................................................. 47

Table 11: Additive Latency (AL) Settings ......................................................................................................... 49

Table 12: TDQS Function Matrix .................................................................................................................... 50

Table 13: Address Pin Mapping ...................................................................................................................... 51

Table 14: MR2 Register Definition .................................................................................................................. 51

Table 15: Address Pin Mapping ...................................................................................................................... 54

Table 16: MR3 Register Definition .................................................................................................................. 54

Table 17: Address Pin Mapping ...................................................................................................................... 57

Table 18: MR4 Register Definition .................................................................................................................. 57

Table 19: Address Pin Mapping ...................................................................................................................... 61

Table 20: MR5 Register Definition .................................................................................................................. 61

Table 21: Address Pin Mapping ...................................................................................................................... 64

Table 22: MR6 Register Definition .................................................................................................................. 64

Table 23: Truth Table â Command .................................................................................................................. 66

Table 24: Truth Table â CKE ........................................................................................................................... 68

Table 25: MR Settings for Leveling Procedures ................................................................................................ 76

Table 26: DRAM TERMINATION Function in Leveling Mode ........................................................................... 76

Table 27: Auto Self Refresh Mode ................................................................................................................... 85

Table 28: MR3 Setting for the MPR Access Mode ............................................................................................. 87

Table 29: DRAM Address to MPR UI Translation ............................................................................................. 87

Table 30: MPR Page and MPRx Definitions ..................................................................................................... 88

Table 31: MPR Readout Serial Format ............................................................................................................. 90

Table 32: MPR Readout â Parallel Format ....................................................................................................... 91

Table 33: MPR Readout Staggered Format, x4 ................................................................................................. 92

Table 34: MPR Readout Staggered Format, x4 â Consecutive READs ................................................................ 92

Table 35: MPR Readout Staggered Format, x8 and x16 ..................................................................................... 93

Table 36: Mode Register Setting for CA Parity ................................................................................................. 108

Table 37: VREFDQ Range and Levels ................................................................................................................ 118

Table 38: VREFDQ Settings (VDDQ = 1.2V) ......................................................................................................... 124

Table 39: Connectivity Mode Pin Description and Switching Levels ................................................................ 126

Table 40: PPR MR0 Guard Key Settings .......................................................................................................... 130

Table 41: DDR4 hPPR Timing Parameters DDR4-1600 through DDR4-3200 ..................................................... 133

Table 42: sPPR Associated Rows .................................................................................................................... 134

Table 43: PPR MR0 Guard Key Settings .......................................................................................................... 135

Table 44: DDR4 sPPR Timing Parameters DDR4-1600 through DDR4-3200 ..................................................... 136

Table 45: DDR4 Repair Mode Support Identifier ............................................................................................ 136

Table 46: MAC Encoding of MPR Page 3 MPR3 ............................................................................................... 138

Table 47: Normal tREFI Refresh (TCR Disabled) ............................................................................................. 142

Table 48: Normal tREFI Refresh (TCR Enabled) .............................................................................................. 143

Table 49: MRS Definition .............................................................................................................................. 144

Table 50: REFRESH Command Truth Table .................................................................................................... 144

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4gb_ddr4_dram.pdf - Rev. G 1/17 EN

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