MT40A1G4HX-093E Datasheet, PDF (74/365 Pages) Micron Technology – 4Gb: x4, x8, x16 DDR4 SDRAM

4Gb: x4, x8, x16 DDR4 SDRAM
Input Clock Frequency Change
2. Enter SR.
3. Change frequency.
4. Clock must be stable ^tCKSRX.
5. Exit SR.
6. Set DLL to on by setting MR1 to A0 = 0.
7. Update mode registers.
8. Issue any valid command.
Input Clock Frequency Change
After the device is initialized, it requires the clock to be stable during almost all states of
normal operation. This means that after the clock frequency has been set and is in the
stable state, the clock period is not allowed to deviate except for what is allowed by the
clock jitter and spread spectrum clocking (SSC) specifications. The input clock frequen-
cy can be changed from one stable clock rate to another stable clock rate only when in
self refresh mode. Outside of self refresh mode, it is illegal to change the clock frequen-
cy.
After the device has been successfully placed in self refresh mode and ^tCKSRE/
t_{CKSRE_PAR have been satisfied, the state of the clock becomes a "Don’t Care." Follow-}
ing a "Don’t Care," changing the clock frequency is permissible, provided the new clock
frequency is stable prior to ^tCKSRX. When entering and exiting self refresh mode for the
sole purpose of changing the clock frequency, the self refresh entry and exit specifica-
tions must still be met as outlined in SELF REFRESH Operation.
For the new clock frequency, additional MRS commands to MR0, MR2, MR3, MR4, MR5,
and MR6 may need to be issued to program appropriate CL, CWL, gear-down mode,
READ and WRITE preamble, Command Address Latency, and ^tCCD_L/^tDLLK values.
When the clock rate is being increased (faster), the MR settings that require additional
clocks should be updated prior to the clock rate being increased. In particular, the PL
latency must be disabled when the clock rate changes, ie. while in self refresh mode. For
example, if changing the clock rate from DDR4-2133 to DDR4-2933 with CA parity
mode enabled, MR5[2:0] must first change from PL = 4 to PL = disable prior to PL = 6.
The correct procedure would be to (1) change PL = 4 to disable via MR5 [2:0], (2) enter
self refresh mode, (3) change clock rate from DDR4-2133 to DDR4-2933, (4) exit self re-
fresh mode, (5) Enable CA parity mode setting PL = 6 vis MR5 [2:0].
If the MR settings that require additional clocks are updated after the clock rate has
been increased, for example. after exiting self refresh mode, the required MR settings
must be updated prior to removing the DRAM from the IDLE state, unless the DRAM is
RESET. If the DRAM leaves the IDLE state to enter self refresh mode or ZQ Calibration,
the updating of the required MR settings may be deferred to the next time the DRAM
enters the IDLE state.
If MR6 is issued prior to self refresh entry for new the ^tDLLK value, DLL will relock auto-
matically at self refresh exit. However, if MR6 is issued after self refresh entry, MR0 must
be issued to reset the DLL.
The device input clock frequency can change only within the minimum and maximum
operating frequency specified for the particular speed grade. Any frequency change be-
low the minimum operating frequency would require the use of DLL-on mode to DLL-
off mode transition sequence (see DLL-On/Off Switching Procedures).
09005aef84af6dd0
4gb_ddr4_dram.pdf - Rev. G 1/17 EN
74
Micron Technology, Inc. reserves the right to change products or specifications without notice.
‹ 2014 Micron Technology, Inc. All rights reserved.