MT40A1G4HX-093E Datasheet, PDF (115/365 Pages) Micron Technology – 4Gb: x4, x8, x16 DDR4 SDRAM

4Gb: x4, x8, x16 DDR4 SDRAM
Per-DRAM Addressability
Figure 59: PDA Operation Enabled, BL8
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&.BW
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056
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2'7
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W _02'
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Note: 1. R_TT(Park) = Enable; R_TT(NOM) = Enable; WRITE preamble set = 2^tCK; and DLL = On.
Figure 60: PDA Operation Enabled, BC4
CK_c
CK_t
MR3 A4 = 1
(PDA enable) ^MRS
DQS_t
DQS_c
DQ0
ODT
R_TT
t_MOD
MRS
CWL+AL+PL
t_{MRD_PDA}
MRS
t_{PDA_S}
DODTLoff = WL-3
t_{PDA_H}
DODTLon = WL-3
R_TT(Park)
R_TT(NOM)
R_TT(Park)
Note: 1. R_TT(Park) = Enable; R_TT(NOM) = Enable; WRITE preamble set = 2^tCK; and DLL = On.
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4gb_ddr4_dram.pdf - Rev. G 1/17 EN
115
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