MT40A1G4HX-093E Datasheet, PDF (204/365 Pages) Micron Technology – 4Gb: x4, x8, x16 DDR4 SDRAM

4Gb: x4, x8, x16 DDR4 SDRAM
READ Operation
4. BL8 setting activated by either MR0[1:0] = 00 or MR0[1:0] = 01 and A12 = 1 during READ
commands at T0 and WRITE commands at T8.
5. When operating in 2^tCK WRITE preamble mode, CWL may need to be programmed to a
value at least 1 clock greater than the lowest CWL setting.
6. CA parity = Disable, CS to CA latency = Disable, Read DBI = Disable, Write DBI = Disable,
Write CRC = Disable.
Figure 141: READ (BC4) OTF to WRITE (BC4) OTF with 1^tCK Preamble in Same or Different Bank
Group
T0
T1
T5
T6
T7
T8
T9
T10
T11
T12
T13
T14
T15
T16
T17
T18
T19
T20
CK_c
CK_t
Command READ
DES
DES
WRITE
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
t_WR
READ to WRITE command delay
= RL +BL/2 - WL + 2 ^tCK
4 Clocks
t_WTR
Bank Group
BGa
Address
BGa or
BGb
Address
Bank
Col n
DQS_t,
DQS_c
DQ
Bank
Col b
RL = 11
t_RPRE
t_RPST
t_WPRE
t_WPST
DO DO DO DO
n n+1 n+2 n+3
WL = 9
DI DI DI DI
b b+1 b+2 b+3
Time Break
Transitioning Data
Don’t Care
Notes:
1. BC = 4, RL = 11 (CL = 11, AL = 0), READ preamble = 1^tCK, WL = 9 (CWL = 9, AL = 0),
WRITE preamble = 1^tCK.
2. DO n = data-out from column n; DI b = data-in from column b.
3. DES commands are shown for ease of illustration; other commands may be valid at
these times.
4. BC4 (OTF) setting activated by MR0[1:0] = 01 and A12 = 0 during READ commands at T0
and WRITE commands at T6.
5. CA parity = Disable, CS to CA latency = Disable, Read DBI = Disable, Write DBI = Disable,
Write CRC = Disable.
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4gb_ddr4_dram.pdf - Rev. G 1/17 EN
204
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