MT40A1G4HX-093E Datasheet, PDF (105/365 Pages) Micron Technology – 4Gb: x4, x8, x16 DDR4 SDRAM

4Gb: x4, x8, x16 DDR4 SDRAM
Maximum Power-Saving Mode
shown in the figure below. Because the clock receivers (CK_t, CK_c) are disabled during
this mode, CS_n = LOW is captured by the rising edge of the CKE signal. If the CS_n sig-
nal level is detected LOW, the DRAM clears the maximum power-saving mode MRS bit
and begins the exit procedure from this mode. The external clock must be restarted and
be stable by ^tCKMPX before the device can exit the maximum power-saving mode. Dur-
ing the exit time (^tXMP), only NOP and DES commands are allowed: NOP during
t_{MPX_LH and DES the remainder of} t_{XMP. After} t_{XMP expires, valid commands not re-}
quiring a locked DLL are allowed; after ^tXMP_DLL expires, valid commands requiring a
locked DLL are allowed.
Figure 47: Maximum Power-Saving Mode Exit
Ta0
Ta1
Ta2
Ta3
Tb0
Tb1
Tb2
Tb3
Tc0
Tc1
Tc2
Tc4
Td0
Td1
Td2
Td3
Te0
Te1
CK_c
CK_t
t_CKMPX
Command
CS_n
CKE
NOP
NOP
NOP
NOP
NOP
DES
DES
DES
DES
Valid
DES
DES
t_{MPX_LH}
t_{MPX_S}
t_XMP
t_{XMP_DLL}
RESET_n
Time Break
Don’t Care
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4gb_ddr4_dram.pdf - Rev. G 1/17 EN
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