MT40A1G4HX-093E Datasheet, PDF (187/365 Pages) Micron Technology – 4Gb: x4, x8, x16 DDR4 SDRAM

4Gb: x4, x8, x16 DDR4 SDRAM
Bank Access Operation
Figure 118: ^tRRD Timing
CK_c
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
CK_t
Command
ACT
DES
DES
DES
ACT
DES
DES
DES
DES
DES
ACT
DES
t_{RRD_S}
t_{RRD_L}
Bank
Group BG a
BG b
(BG)
BG b
Bank Bank c
Bank c
Bank d
Address Row n
Row n
Row n
Don’t Care
Notes:
1. ^tRRD_S; ACTIVATE-to-ACTIVATE command period (short); applies to consecutive ACTI-
VATE commands to different bank groups (T0 and T4).
2. ^tRRD_L; ACTIVATE-to-ACTIVATE command period (long); applies to consecutive ACTI-
VATE commands to the different banks in the same bank group (T4 and T10).
Figure 119: ^tWTR_S Timing (WRITE-to-READ, Different Bank Group, CRC and DM Disabled)
T0
T1
T2
Ta0
Ta1
Ta2
Ta3
Ta4
Ta5
Ta6
Ta7
Tb0
Tb1
CK_c
CK_t
Command WRITE
Valid
Valid
Bank
Group
BGa
Bank Bank c
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
t_{WTR_S}
READ
BGb
Bank c
Valid
Address Col n
DQS, DQS_c
t_WPRE
t_WPST
Col n
DQ
DI DI DI DI DI DI DI DI
n n+1 n+2 n+3 n+4 n+5 n+6 n+7
WL
RL
Time Break
Transitioning Data
Don’t Care
Note: 1. ^tWTR_S: delay from start of internal write transaction to internal READ command to a
different bank group.
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4gb_ddr4_dram.pdf - Rev. G 1/17 EN
187
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