MT40A1G4HX-093E Datasheet, PDF (179/365 Pages) Micron Technology – 4Gb: x4, x8, x16 DDR4 SDRAM

4Gb: x4, x8, x16 DDR4 SDRAM
Programmable Preamble Modes and DQS Postambles
Programmable Preamble Modes and DQS Postambles
The device supports programmable WRITE and READ preamble modes, either the nor-
mal 1^tCK preamble mode or special 2^tCK preamble mode. The 2^tCK preamble mode
places special timing constraints on many operational features as well as being suppor-
ted for data rates of DDR4-2400 and faster. The WRITE preamble 1^tCK or 2^tCK mode
can be selected independently from READ preamble 1^tCK or 2^tCK mode.
READ preamble training is also supported; this mode can be used by the DRAM con-
troller to train or "read level" the DQS receivers.
There are ^tCCD restrictions under some circumstances:
• When 2^tCK READ preamble mode is enabled, a ^tCCD_S or ^tCCD_L of 5 clocks is not
allowed.
• When 2^tCK WRITE preamble mode is enabled and write CRC is not enabled, a ^tCCD_S
or ^tCCD_L of 5 clocks is not allowed.
• When 2^tCK WRITE preamble mode is enabled and write CRC is enabled, a ^tCCD_S or
t_{CCD_L of 6 clocks is not allowed.}
WRITE Preamble Mode
MR4[12] = 0 selects 1^tCK WRITE preamble mode while MR4[12] = 1 selects 2^tCK WRITE
preamble mode. Examples are shown in the figures below.
Figure 107: 1^tCK vs. 2^tCK WRITE Preamble Mode
1^tCK Mode
WR
CK_c
CK_t
DQS_t,
DQS_c
WL
Preamble
DQ
2^tCK Mode
WR
CK_c
CK_t
DQS_t,
DQS_c
D0 D1 D2 D3 D4 D5 D6 D7
WL
Preamble
DQ
D0 D1 D2 D3 D4 D5 D6 D7
09005aef84af6dd0
4gb_ddr4_dram.pdf - Rev. G 1/17 EN
179
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