MT40A256M16GE-062E Datasheet, PDF (46/365 Pages) Micron Technology – 4Gb: x4, x8, x16 DDR4 SDRAM

4Gb: x4, x8, x16 DDR4 SDRAM
Mode Register 0
CAS Latency
The CAS latency (CL) setting is defined in the MR0 Register Definition table. CAS laten-
cy is the delay, in clock cycles, between the internal READ command and the availability
of the first bit of output data. The device does not support half-clock latencies. The
overall read latency (RL) is defined as additive latency (AL) + CAS latency (CL): RL = AL +
CL.
Test Mode
The normal operating mode is selected by MR0[7] and all other bits set to the desired
values shown in the MR0 Register Definition table. Programming MR0[7] to a value of 1
places the device into a DRAM manufacturer-defined test mode to be used only by the
manufacturer, not by the end user. No operations or functionality is specified if MR0[7]
= 1.
Write Recovery(WR)/READ-to-PRECHARGE
The programmed write recovery (WR) value is used for the auto precharge feature along
with ^tRP to determine ^tDAL. WR for auto precharge (MIN) in clock cycles is calculated
by dividing ^tWR (in ns) by ^tCK (in ns) and rounding up to the next integer: WR (MIN)
cycles = roundup (^tWR[ns]/^tCK[ns]). The WR value must be programmed to be equal to
or larger than ^tWR (MIN). When both DM and write CRC are enabled in the mode regis-
ter, the device calculates CRC before sending the write data into the array; ^tWR values
will change when enabled. If there is a CRC error, the device blocks the WRITE opera-
tion and discards the data.
Internal READ-to-PRECHARGE (RTP) command delay for auto precharge (MIN) in
clock cycles is calculated by dividing ^tRTP (in ns) by ^tCK (in ns) and rounding up to the
next integer: RTP (MIN) cycles = roundup (^tRTP[ns]/^tCK[ns]). The RTP value in the
mode register must be programmed to be equal to or larger than RTP (MIN). The pro-
grammed RTP value is used with ^tRP to determine the ACT timing to the same bank.
DLL RESET
The DLL reset bit is self-clearing, meaning that it returns to the value of 0 after the DLL
RESET function has been issued. After the DLL is enabled, a subsequent DLL RESET
should be applied. Any time the DLL RESET function is used, ^tDLLK must be met before
functions requiring the DLL can be used, such as READ commands or synchronous
ODT operations, for example,).
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4gb_ddr4_dram.pdf - Rev. G 1/17 EN
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