MT40A256M16GE-062E Datasheet, PDF (222/365 Pages) Micron Technology – 4Gb: x4, x8, x16 DDR4 SDRAM

Figure 164: Rx Compliance Mask
4Gb: x4, x8, x16 DDR4 SDRAM
WRITE Operation
Rx Mask
V_{CENTDQ,midpoint}
TdiVW
V_{CENTDQ,midpoint} is defined as the midpoint between the largest V_REFDQ voltage level and
the smallest V_REFDQ voltage level across all DQ pins for a given DRAM. Each DQ pin's
V_REFDQ is defined by the center (widest opening) of the cumulative data input eye as de-
picted in the following figure. This means a DRAM's level variation is accounted for
within the DRAM Rx mask. The DRAM V_REFDQ level will be set by the system to account
for R_ON and ODT settings.
Figure 165: V_{CENT_DQ} V_REFDQ Voltage Variation
DQx
DQy
(smallest V_REFDQ Level)
DQz
(largest V_REFDQ Level)
V_CENTDQx
V_CENTDQy
V_CENTDQz
V_{CENTDQ,midpoint}
V_REF variation
(component)
The following figure shows the Rx mask requirements both from a midpoint-to-mid-
point reference (left side) and from an edge-to-edge reference. The intent is not to add
any new requirement or specification between the two but rather how to convert the
relationship between the two methodologies. The minimum data-eye shown in the
composite view is not actually obtainable due to the minimum pulse width require-
ment.
09005aef84af6dd0
4gb_ddr4_dram.pdf - Rev. G 1/17 EN
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