MT40A256M16GE-062E Datasheet, PDF (199/365 Pages) Micron Technology – 4Gb: x4, x8, x16 DDR4 SDRAM

4Gb: x4, x8, x16 DDR4 SDRAM
READ Operation
Figure 131: Nonconsecutive READ (BL8) with 1^tCK Preamble in Same or Different Bank Group
T0
CK_c
CK_t
T1
T2
T3
T4
T5
T10
T11
T12
T13
T14
T15
T16
T17
T18
T19
T20
T21
Command READ
Bank Group
Address
BGa
Address
Bank
Col n
DQS_t,
DQS_c
DQ
DES
DES
DES
DES
READ
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
t_{CCD_S/L = 5}
BGb
Bank
Col b
t_RPRE
t_RPST
RL = 11
DO DO DO DO DO DO DO DO
n n+1 n+2 n+3 n+4 n+5 n+6 n+7
RL = 11
DO DO DO DO DO DO DO DO
b b+1 b+2 b+3 b+4 b+5 b+6 b+7
Time Break
Transitioning Data
Don’t Care
Notes:
1. BL8, AL = 0, CL = 11, Preamble = 1^tCK, ^tCCD_S/L = 5.
2. DO n (or b) = data-out from column n (or column b).
3. DES commands are shown for ease of illustration; other commands may be valid at
these times.
4. BL8 setting activated by either MR0[1:0] = 00 or MR0[1:0] = 01 and A12 = 1 during READ
commands at T0 and T5.
5. CA parity = Disable, CS to CA latency = Disable, Read DBI = Disable.
Figure 132: Nonconsecutive READ (BL8) with 2^tCK Preamble in Same or Different Bank Group
T0
CK_c
CK_t
T1
T2
T5
T6
T9
T10
T11
T12
T13
T14
T15
T16
T17
T18
T19
T20
T21
Command READ
Bank Group
Address
BGa
Address
Bank
Col n
DQS_t,
DQS_c
DQ
DES
DES
DES
READ
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
t_{CCD_S/L = 6}
BGa or
BGb
Bank
Col b
t_RPRE
t_RPRE
t_RPST
RL = 11
DO DO DO DO DO DO DO DO
n n+1 n+2 n+3 n+4 n+5 n+6 n+7
RL = 11
DO DO DO DO DO DO DO DO
b b+1 b+2 b+3 b+4 b+5 b+6 b+7
Time Break
Transitioning Data
Don’t Care
Notes:
1. BL8, AL = 0, CL = 11, Preamble = 2^tCK, ^tCCD_S/L = 6.
2. DO n (or b) = data-out from column n (or column b).
3. DES commands are shown for ease of illustration; other commands may be valid at
these times.
4. BL8 setting activated by either MR0[A1:0 = 00] or MR0[A1:0 = 01] and A12 = 1 during
READ commands at T0 and T6.
5. CA parity = Disable, CS to CA latency = Disable, Read DBI = Disable.
6. 6 ^tCCD_S/L = 5 isn’t allowed in 2^tCK preamble mode.
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4gb_ddr4_dram.pdf - Rev. G 1/17 EN
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