MT40A256M16GE-062E Datasheet, PDF (234/365 Pages) Micron Technology – 4Gb: x4, x8, x16 DDR4 SDRAM

4Gb: x4, x8, x16 DDR4 SDRAM
WRITE Operation
4. BL8 setting activated by either MR0[1:0] = 00 or MR0[1:0] = 01 and A12 = 1 during
WRITE command at T0 and READ command at T15.
5. CA parity = Disable, CS to CA latency = Disable, Read DBI = Disable, Write DBI = Disable,
Write CRC = Disable.
6. The write timing parameter (^tWTR_S) is referenced from the first rising clock edge after
the last write data shown at T13.
Figure 181: WRITE (BL8) to READ (BL8) with 1^tCK Preamble in Same Bank Group
T0
T1
T7
T8
T9
T10
T11
T12
T13
T14
T15
T16
T17
T18
T26
T27
T28
T29
CK_c
CK_t
Command WRITE
Bank Group
BGa
Address
Address
Bank
Col n
DQS_t,
DQS_c
DQ
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
4 Clocks
t_{WTR_L = 4}
WL = AL + CWL = 9
t_WPRE
t_WPST
DI DI DI DI DI DI DI DI
n n+1 n+2 n+3 n+4 n+5 n+6 n+7
READ
BGa
Bank
Col b
DES
DES
DES
DES
DES
t_RPRE
RL = AL + CL = 11
DI DI DI
b b+1 b+2
Time Break
Transitioning Data
Don’t Care
Notes:
1. BL = 8, WL = 9 (CWL = 9, AL = 0), CL = 11, READ preamble = 1^tCK, WRITE preamble =
1^tCK.
2. DI b = data-in from column b.
3. DES commands are shown for ease of illustration; other commands may be valid at
these times.
4. BL8 setting activated by either MR0[1:0] = 00 or MR0[1:0] = 01 and A12 = 1 during
WRITE command at T0 and READ command at T17.
5. CA parity = Disable, CS to CA latency = Disable, Read DBI = Disable, Write DBI = Disable,
Write CRC = Disable.
6. The write timing parameter (^tWTR_L) is referenced from the first rising clock edge after
the last write data shown at T13.
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4gb_ddr4_dram.pdf - Rev. G 1/17 EN
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