MT40A256M16GE-062E Datasheet, PDF (127/365 Pages) Micron Technology – 4Gb: x4, x8, x16 DDR4 SDRAM

4Gb: x4, x8, x16 DDR4 SDRAM
Connectivity Test Mode
Logic Equations for a x8 Device, When Supported
DQ0 = MT0
DQ1 = MT1
DQ2 = MT2
DQ3 = MT3
DQ4 = MT4
DQ5 = MT5
DQ6 = MT6
DQ7 = MT7
DQS_t = MT8
DQS_c = MT9
Logic Equations for a x16 Device
DQ0 = MT0
DQ10 = INV DQ2
DQ1 = MT1
DQ11 = INV DQ3
DQ2 = MT2
DQ12 = INV DQ4
DQ3 = MT3
DQ13 = INV DQ5
DQ4 = MT4
DQ14 = INV DQ6
DQ5 = MT5
DQ15 = INV DQ7
DQ6 = MT6
LDQS_t = MT8
DQ7 = MT7
LDQS_c = MT9
DQ8 = INV DQ0 UDQS_t = INV LDQS_t
DQ9 = INV DQ1 UDQS_c = INV LDQS_c
CT Input Timing Requirements
Prior to the assertion of the TEN pin, all voltage supplies, including VrefCA, must be val-
id and stable and RESET_n registered High prior to entering CT mode. Upon the asser-
tion of the TEN pin HIGH with RESET_n, CKE and CS_n held HIGH; CLK_t, CLK_c, and
CKE signals become test inputs within ^tCTECT_Valid. The remaining CT inputs become
valid ^tCT_Enable after TEN goes HIGH when CS_n allows input to begin sampling, pro-
vided inputs were valid for at least ^tCT_Valid. While in CT mode, refresh activities in the
memory arrays are not allowed; they are initiated either externally (auto refresh) or in-
ternally (self refresh).
The TEN pin may be asserted after the DRAM has completed power-on. After the DRAM
is initialized and V_REFDQ is calibrated, CT mode may no longer be used. The TEN pin
may be de-asserted at any time in CT mode. Upon exiting CT mode, the states and the
integrity of the original content of the memory array are unknown. A full reset of the
memory device is required.
After CT mode has been entered, the output signals will be stable within ^tCT_Valid after
the test inputs have been applied as long as TEN is maintained HIGH and CS_n is main-
tained LOW.
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4gb_ddr4_dram.pdf - Rev. G 1/17 EN
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