MT40A256M16GE-062E Datasheet, PDF (19/365 Pages) Micron Technology – 4Gb: x4, x8, x16 DDR4 SDRAM

4Gb: x4, x8, x16 DDR4 SDRAM
General Notes and Description
General Notes and Description
Description
The DDR4 SDRAM is a high-speed dynamic random-access memory internally config-
ured as an eight-bank DRAM for the x16 configuration and as a 16-bank DRAM for the
x4 and x8 configurations. The DDR4 SDRAM uses an 8n-prefetch architecture to ach-
ieve high-speed operation. The 8n-prefetch architecture is combined with an interface
designed to transfer two data words per clock cycle at the I/O pins.
A single READ or WRITE operation for the DDR4 SDRAM consists of a single 8n-bit
wide, four-clock data transfer at the internal DRAM core and two corresponding n-bit
wide, one-half-clock-cycle data transfers at the I/O pins.
Industrial Temperature
An industrial temperature (IT) device option requires that the case temperature not ex-
ceed below –40°C or above 95°C. JEDEC specifications require the refresh rate to double
when T_C exceeds 85°C; this also requires use of the high-temperature self refresh option.
Additionally, ODT resistance and the input/output impedance must be derated when
operating outside of the commercial temperature range, when T_C is between –40°C and
0°C.
General Notes
• The functionality and the timing specifications discussed in this data sheet are for the
DLL enable mode of operation (normal operation), unless specifically stated other-
wise.
• Throughout the data sheet, the various figures and text refer to DQs as "DQ." The DQ
term is to be interpreted as any and all DQ collectively, unless specifically stated oth-
erwise.
• The terms "_t" and "_c" are used to represent the true and complement of a differen-
tial signal pair. These terms replace the previously used notation of "#" and/or over-
bar characters. For example, differential data strobe pair DQS, DQS# is now referred
to as DQS_t, DQS_c.
• The term "_n" is used to represent a signal that is active LOW and replaces the previ-
ously used "#" and/or overbar characters. For example: CS# is now referred to as
CS_n.
• The terms "DQS" and "CK" found throughout the data sheet are to be interpreted as
DQS_t, DQS_c and CK_t, CK_c respectively, unless specifically stated otherwise.
• Complete functionality may be described throughout the entire document; any page
or diagram may have been simplified to convey a topic and may not be inclusive of all
requirements.
• Any specific requirement takes precedence over a general statement.
• Any functionality not specifically stated here within is considered undefined, illegal,
and not supported, and can result in unknown operation.
• Addressing is denoted as BG[n] for bank group, BA[n] for bank address, and A[n] for
row/col address.
• The NOP command is not allowed, except when exiting maximum power savings
mode or when entering gear-down mode, and only a DES command should be used.
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4gb_ddr4_dram.pdf - Rev. G 1/17 EN
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