MT40A256M16GE-062E Datasheet, PDF (20/365 Pages) Micron Technology – 4Gb: x4, x8, x16 DDR4 SDRAM

4Gb: x4, x8, x16 DDR4 SDRAM
General Notes and Description
• Not all features described within this document may be available on the Rev. A (first)
version.
• Not all specifications listed are finalized industry standards; best conservative esti-
mates have been provided when an industry standard has not been finalized.
• Although it is implied throughout the specification, the DRAM must be used after V_DD
has reached the stable power-on level, which is achieved by toggling CKE at least once
every 8192 × ^tREFI. However, in the event CKE is fixed HIGH, toggling CS_n at least
once every 8192 × ^tREFI is an acceptable alternative. Placing the DRAM into self re-
fresh mode also alleviates the need to toggle CKE.
• Not all features designated in the data sheet may be supported by earlier die revisions
due to late definition by JEDEC.
Definitions of the Device-Pin Signal Level
• HIGH: A device pin is driving the logic 1 state.
• LOW: A device pin is driving the logic 0 state.
• High-Z: A device pin is tri-state.
• ODT: A device pin terminates with the ODT setting, which could be terminating or tri-
state depending on the mode register setting.
Definitions of the Bus Signal Level
• HIGH: One device on the bus is HIGH, and all other devices on the bus are either ODT
or High-Z. The voltage level on the bus is nominally V _DDQ.
• LOW: One device on the bus is LOW, and all other devices on the bus are either ODT
or High-Z. The voltage level on the bus is nominally V _OL(DC) if ODT was enabled, or
V_SSQ if High-Z.
• High-Z: All devices on the bus are High-Z. The voltage level on the bus is undefined as
the bus is floating.
• ODT: At least one device on the bus is ODT, and all others are High-Z. The voltage lev-
el on the bus is nominally V_DDQ.
• The specification requires 8,192 refresh commands within 64ms between 0 ^oC and 85
o_{C. This allows for a} t_{REFI of 7.8125μs (the use of "7.8μs" is truncated from 7.8125μs).}
The specification also requires 8,192 refresh commands within 32ms between 85 ^oC
and 95 ^oC. This allows for a ^tREFI of 3.90625μs (the use of "3.9μs" is truncated from
3.90625μs).
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4gb_ddr4_dram.pdf - Rev. G 1/17 EN
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